參數(shù)資料
型號: ADD8502
廠商: Analog Devices, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:128; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:25-35
中文描述: 整合式LCD灰度發(fā)生器
文件頁數(shù): 6/16頁
文件大小: 1436K
代理商: ADD8502
REV. 0
ADD8502
–6–
Pin No.
Mnemonic
Name
I/O Description
21
REV2
Reference Output
Select
I
When
PSK
is HIGH and GS1 or GS2 is LOW, then INVERT selects the output
levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to
reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4
are connected to reference levels VN0 to VN4, respectively. When
PSK
is HIGH
and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still
connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0
and V4 switch to VN0 and VN4 when REV is LOW.
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2
leave the outputs of A1 to A3 fully active.
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the
outputs of A1 to A3 fully active.
When
PSK
is pulled LOW, the chip will be put into the full Power-Down Mode.
The DACs, resistor ladder network preamps, and output buffers will all be shut
down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to
normal operation is within 30
μ
s.
22
GS2
Sleep Mode
Select
I
23
GS1
Sleep Mode
Select
I
24
PSK
Global Power
Shutdown
I
All digital inputs accept CMOS or TTL logic levels.
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