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參數(shù)資料
| 型號： | ADD8502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:25-35 |
| 中文描述： | 整合式LCD灰度發(fā)生器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 1436K |
| 代理商： | ADD8502 |
REV. 0
ADD8502
–12–
Table II. DAC Control Function
Control Code
C3
C2 C1 C0
Input Register
Status
DAC Register
(Sleep/Wake)
Power-Down Status
Comments
Status
0
0
0
0
No Change
No Update
No Change
No operation; power-down status unchanged
(part stays in Wake or Sleep Mode).
0
0
0
1
Load DAC A
No Update
No Change
Load input Register A with data. DAC outputs
unchanged. Power-down status unchanged.
0
0
1
0
Load DAC B
No Update
No Change
Load input Register B with data. DAC outputs
unchanged. Power-down status unchanged.
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Not Used
Not Used
Not Used
Not Used
Not Used
1
0
0
0
No Change
Update Outputs
Wake
Load both DAC registers with existing contents
of input registers. Update DAC outputs. Part
wakes up.
1
0
0
1
Load DAC A
Update Outputs
Wake
Load input Register A. Load DAC registers with
new contents of input register A and existing
contents of Register B. Update DAC outputs.
Part wakes up.
1
0
1
0
Load DAC B
Update Outputs
Wake
Load input Register B. Load DAC registers with
new contents of input Register B and existing
contents of Register A. Update DAC outputs.
Part wakes up.
1
1
0
1
1
0
1
0
Not Used
Not Used
1
1
0
1
No Change
No Update
Wake
Part wakes up. Input and DAC registers
unchanged. DAC outputs reflect existing
contents of DAC registers.
1
1
1
0
No Change
No Update
Sleep
Power down the IC, put in into Sleep Mode.
1
1
1
1
Load DACs
A, B with Same
10-Bit Code
Update
Outputs
Wake
Load both input registers. Load both DAC
registers with new contents of input registers.
Update DAC outputs. Part wakes up.
Modes of Operation
The ADD8502 has various modes of operation, such as updating
both DACs simultaneously or changing the power-down status
(Sleep/Wake). These are selected by writing the appropriate
4-bit control code (C0–C3). The details for each mode are
summarized in Table II.
Low Power Serial Interface
To reduce the power consumption of the device ever further, the
interface only powers up fully when the device is being written
to. As soon as the 16-bit control word has been written to the
part, the SCK and D
IN
input buffers are powered down. They
only power up again following a falling edge of
CS-LD
.
Double-Buffered Interface
The ADD8502 has double-buffered interfaces consisting of two
banks of registers: input and DAC. The input register is con-
nected directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC register contains the digital
code used by the resistor string.
Access to the DAC register is controlled by the control codes,
C0 to C3. The user can update both DACs simultaneously as
well as individually. It depends on the selected control codes to
update individual output or both outputs simultaneously.
Initial Power-Up Condition
The ADD8502 has preset DAC conditions when its initially
powered on. The DACs are loaded with 1110 1011 11 for the
upper DAC and 0000 1010 00 for the lower DAC. The part is
powered up in a normal operation mode (Wake Status).
Power-Down Modes
The ADD8502 has two shutdown modes. One mode is to fully
shut down the device using
PSK
or the digital serial control code,
and the other mode is to shut down V1 to V3 buffers using GS1
and GS2. See Table III for the priority of the shutdown control
functions.
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