參數(shù)資料
型號: ADD8502
廠商: Analog Devices, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:128; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:25-35
中文描述: 整合式LCD灰度發(fā)生器
文件頁數(shù): 5/16頁
文件大?。?/td> 1436K
代理商: ADD8502
REV. 0
ADD8502
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Name
I/O
Description
1
2
V
L
D
IN
Logic Select Pin
Serial Data Input
I
I
Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to V
DD.
When CS is LOW, the input on this pin is shifted into the internal shift register on
the rising edge of SCK.
Accepts up to 10 MHz input. The rising edge on this clock will shift the data on
D
IN
Pin into the internal shift registers.
When
CS-LD
is LOW, SCK is enabled for shifting data on the D
IN
input into the
internal shift register on the rising edge of SCK. Data is loaded MSB first.
When CM is LOW, COM will output the voltage level input on COM_M.
When CM is HIGH, COM levels will be determined by the input on REV1.
If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is
connected to COM and op amp A4 is shut down. Refer to Table II.
With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level
input at V
DD
. A LOW on REV1 will cause COM to output the voltage level input
at GND.
Unused Pin
Unused Pin
If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH,
COM will output the voltage input at V
DD
when REV1 is HIGH and will output
the voltage input at GND when REV1 is LOW. Refer to Table II.
COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may
be the system 3.3 V supply.
Unused Pin
Ground. Nominally 0 V.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When
PSK
is LOW, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When
PSK
is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When
PSK
is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When
PSK
is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When
PSK
is LOW, these outputs will be Hi-Z.
Supply Voltage. Nominally 5 V.
Unused Pin
3
SCK
Serial Clock
I
4
CS-LD
Load
I
5
CM
Logic Control 2
for V
COM
Logic Control V4
I
6
CV4
I
7
REV1
Logic Control 1
for V
COM
I
8
9
10
NC
NC
COM
No Connect
No Connect
Common Output
O
11
COM_M
Common System
V
REF
No Connect
Ground
Output
I
12
13
14
NC
GND
V4
I
O
15
V3
Output
O
16
V2
Output
O
17
V1
Output
O
18
V0
Output
O
19
20
V
DD
NC
Supply
No Connect
I
PIN CONFIGURATION
V0
V1
V2
V3
V4
GND
18
17
16
15
14
13
PIN 1
(Not to Scale)
24
V
L
D
IN
SCK
CS-LD
CM
CV4
P
G
23
G
22
R
21
N
20
V
D
19
R
N
N
C
C
N
NC = NO CONNECT
ADD8502
7
8
9
10
11
12
1
2
3
4
5
6
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PDF描述
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