參數(shù)資料
型號(hào)： ADC1443D125HD
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual channel 14-bit ADC; 125 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝： ADC1443D125HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù)： 21/50頁
文件大?。?/td> 408K
代理商： ADC1443D125HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
21 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.1.4
Programmable full-scale
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
by programming internal reference gain between 0 dB and
6 dB in 1 dB steps. The
full-scale range can be set independently via bits INTREF[2:0] of the SPI local registers
(see
Table 10
and
Table 24
).
Table 10.
Default values are shown highlighted.
INTREF[2:0]
000
001
010
011
100
101
110
111
11.1.5
Anti-kickback circuitry
An anti-kickback circuitry (RC-filter in
Figure 26
) is required to counteract the effects of the
charge injection generated by the sampling capacitance.
The RC-filter is also used to filter noise from the signal before it reaches the sampling
stage. It is recommended that the capacitor has
a value that maximizes noise attenuation
without degrading the settling time excessively.
Fig 25. Equivalent schematic of the common-mode reference circuit
VCM
0.1
μ
F
PACKAGE
ESD
PARASITICS
001aan473
COMMON MODE
REFERENCE
ADC CORE
Reference gain control
Level (dB)
0
1
2
3
4
5
6
reserved
Full-scale (V (p-p))
2
1.78
1.59
1.42
1.26
1.12
1
x
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