By default, the ADAU1401A is in I2C mode, but" />
參數(shù)資料
型號(hào)： ADAU1401AWBSTZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/52頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
ADAU1401A
Rev. A | Page 26 of 52
SPI PORT
By default, the ADAU1401A is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of the CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of the ADAU1401A on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 19. A timing diagram is shown in Figure 3. All
data should be written MSB first. The ADAU1401A cannot be
taken out of SPI mode without a full reset.
Chip Address, R/W
The first byte of an SPI transaction includes the 7-bit chip address
and an R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1401A devices to share a CLATCH signal, yet
still operate independently. When ADDR0 is low, the chip address
is 0000000; when ADDR0 is high, the address is 0000001 (see
). The LSB of this first byte determines whether the SPI
transaction is a read (Logic Level 1) or a write (Logic Level 0).
Table 18. ADAU1401A SPI Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
ADDR0
R/W
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memory areas or registers. This subaddress is the location of the
appropriate RAM location or register. The MSBs of the subaddress
are zero-padded to bring the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register or
memory location being accessed. During a burst mode write, an
initial subaddress is written followed by a continuous sequence
of data for consecutive memory/register locations. The detailed
data format for continuous mode operation is shown in Table
A sample timing diagram of a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. In Figure 27,
the COUT pin goes from three-state to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 2 contain the
addresses and the R/W bit, and subsequent bytes carry the data.
Table 19. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
CHIP_ADR[6:0], R/W
0000, SUBADR[11:8]
SUBADR[7:0]
Data
1 Continues to end of data.
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
08
50
6-
0
26
Figure 26. SPI Write to ADAU1401A Clocking (Single-Write Mode)
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HIGH-Z
DATA
HIGH-Z
08
50
6-
0
27
BYTE 2
Figure 27. SPI Read from ADAU1401A Clocking (Single-Read Mode)
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