I2
參數(shù)資料
型號(hào)： ADAU1401AWBSTZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/52頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
ADAU1401A
Rev. A | Page 22 of 52
CONTROL PORTS
The ADAU1401A can operate in one of three control modes:
I2C control, SPI control, or self-boot (no external controller).
The ADAU1401A has both a 4-wire SPI control port and a
2-wire I2C bus control port. Either port can be used to set the
RAMs and registers. When the SELFBOOT pin is low at power-
up, the part defaults to I2C mode but can be put into SPI control
mode by pulling the CLATCH/WP pin low three times. When
the SELFBOOT pin is set high at power-up, the ADAU1401A
loads its program, parameters, and register settings from an
external EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory locations and registers. Most signal processing
parameters are controlled by writing new values to the parameter
RAM using the control port. Other functions, such as mute and
input/output mode control, are programmed by writing to the
registers.
All addresses can be accessed in a single-address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1401A. This
subaddress must be two bytes because the memory locations
within the ADAU1401A are directly addressable and their sizes
exceed the range of single-byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in
to
.
The ADAU1401A has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on-the-fly,
the SigmaDSP provides the safeload registers. The safeload
registers can be used to buffer a full set of parameters (for
example, the five coefficients of a biquad) and then transfer
these parameters into the active program within one audio
frame. The safeload mode uses internal logic to prevent
contention between the DSP core and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 15 details these
multiple functions.
Table 15. Control Port Pins and SELFBOOT Pin Functions
Pin
I2C Mode
SPI Mode
Self-Boot
SCL/CCLK
SCL—input
CCLK—input
SCL—output
SDA/COUT
SDA—open-collector output and input
COUT—output
SDA—open-collector output and input
ADDR1/CDATA/WB
ADDR1—input
CDATA—input
WB—writeback trigger
CLATCH/WP
Unused input—tie to ground or IOVDD
CLATCH—input
WP—EEPROM write protect, open-collector output
ADDR0
ADDR0—input
Unused input—tie to ground or IOVDD
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ADAU1401YSTZ 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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