參數(shù)資料
型號: ADATE305BSVZ
廠商: Analog Devices Inc
文件頁數(shù): 37/56頁
文件大小: 0K
描述: IC DCL ATE 250MHZ DUAL 100TQFP
標準包裝: 1
類型: DCL
應(yīng)用: 自動測試設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
ADATE305
Rev. 0 | Page 42 of 56
USER INFORMATION
Table 29. Driver and Load Truth Table1
Registers
Signals
Driver State
Load State
PE Disable
DATA[0]
ADDR[4:0] = 0x0C
Force VT
DATA[1]
ADDR[4:0] = 0x0C
Load Enable
DATA[1]
ADDR[4:0] = 0x0D
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0D
DATAx
RCVx
1
X
High-Z without clamps
Power-down
0
1
X
VT
Power-down
0
VL
Power-down
0
1
High-Z with clamps
Power-down
0
1
0
VH
Power-down
0
1
High-Z with clamps
Power-down
0
1
0
VL
Power-down
0
1
0
1
VT
Power-down
0
1
0
VH
Power-down
0
1
VT
Power-down
0
1
0
VL
Active off
0
1
0
1
High-Z with clamps
Active on
0
1
0
1
0
VH
Active off
0
1
0
1
High-Z with clamps
Active on
0
1
0
VL
Active on
0
1
0
1
High-Z with clamps
Active on
0
1
0
VH
Active on
0
1
High-Z with clamps
Active on
1 X = don’t care.
Table 30. HVOUT Truth Table1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
Channel 0
RCV
Channel 0
DATA
HVOUT Driver Output
1
X
VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
1
0
VL (Channel 0 VL DAC)
1
0
1
VH (Channel 0 VH DAC)
0
X
Disabled (HVOUT pin set to 0 V low impedance)
1 X = don’t care.
Table 31. Comparator Truth Table
Differential
Comparator Enable
DATA[0]
ADDR[4:0] = 0x10
COMP_QH0
COMP_QL0
COMP_QH1
COMP_QL1
0
Normal window mode
Logic high: VOH0 < VDUT0
Logic high: VOL0 < VDUT0
Logic high: VOH1 < VDUT1
Logic high: VOL1 < VDUT1
Logic low: VOH0 > VDUT0
Logic low: VOL0 > VDUT0
Logic low: VOH1 > VDUT1
Logic low: VOL1 > VDUT1
1
Differential comparator mode
Normal window mode
Logic high: VOH0 < VDUT0 VDUT1
Logic high: VOL0 < VDUT0 VDUT1
Logic high: VOH1 < VDUT1
Logic high: VOL1 < VDUT1
Logic low: VOH0 > VDUT0 VDUT1
Logic low: VOL0 > VDUT0 VDUT1
Logic low: VOH1 > VDUT1
Logic low: VOL1 > VDUT1
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