參數(shù)資料
型號： ADATE304BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/52頁
文件大小： 0K
描述： IC DCL ATE 200MHZ DUAL 84CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： DCL
應(yīng)用： 自動測試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 84-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 84-CSPBGA（9x9）
包裝： 托盤
ADATE304
Rev. 0 | Page 45 of 52
RECOMMENDED PMU MODE SWITCHING
SEQUENCES
To minimize any possible aberrations and voltage spikes on the
DUT output, specific mode switching sequences are recommended
for the following transitions:
PMU disable to PMU enable.
PMU force voltage mode to PMU force current mode.
PMU force current mode to PMU force voltage mode.
PMU Disable to PMU Enable
Note that, in Table 39 through Table 49, X indicates the don’t
care bit.
Step 1. Table 39 lists the state of the registers in PMU disabled
mode.
Table 39.
Register
Bits
Setting
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
DATA[2]
0
PMU State
Register, ADDR[4:0]
= 0x0E
DATA[9:8]
XX
DATA[7]
X
DATA[6]
X
DATA[5]
X
DATA[4]
X
DATA[3]
X
DATA[2:0]
XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).
Table 40.
Register
Bits
Setting
Comments
PMU State
Register,
ADDR[4:0] =
0x0E
DATA[9:8]
1X or
00
Set desired input
selection
DATA[7]
X
DATA[6]
X
DATA[5]
X
DATA[4]
X
DATA[3]
0
This bit must be set
to force voltage mode
to reduce aberrations
DATA[2:0]
XXX
Set desired range
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).
Table 41.
Register
Bits
Setting
Comments
PE/PMU Enable
Register,
ADDR[4:0] = 0x0C
DATA[2]
1
PMU is now enabled
in force voltage
mode
PMU Force Voltage Mode to PMU Force Current Mode
Step 1. Table 42 lists the state of registers in force voltage mode.
Table 42.
Register
Bits
Setting
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
DATA[2]
1
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8]
XX
DATA[7]
X
DATA[6]
X
DATA[5]
X
DATA[4]
X
DATA[3]
0
DATA[2:0]
XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).
Table 43.
Register
Bits
Setting
Comments
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8]
01
Set 2.5 V +
DUTGND input
selection
DATA[7]
X
DATA[6]
X
DATA[5]
X
DATA[4]
X
DATA[3]
1
Set to force
current mode
DATA[2:0]
0XX
The 2 μA range
has the
minimum offset
current
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).
Table 44.
Register
Bits
Setting
Comments
VIN 16-Bit DAC,
ADDR[4:0] = 0x0B
DATA[15:0]
X
Update the VIN
16-Bit DAC
register to the
desired value
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).
Table 45.
Register
Bits
Setting
Comments
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8]
1X
Set VIN input
selection
DATA[7]
X
DATA[6]
X
DATA[5]
X
DATA[4]
X
DATA[3]
1
DATA[2:0]
XXX
Set to the
desired current
range
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