參數(shù)資料
型號(hào)： ADATE304BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 38/52頁
文件大小： 0K
描述： IC DCL ATE 200MHZ DUAL 84CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： DCL
應(yīng)用： 自動(dòng)測(cè)試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 84-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 84-CSPBGA（9x9）
包裝： 托盤
ADATE304
Rev. 0 | Page 43 of 52
DETAILS OF DACS vs. LEVELS
There are ten 14-bit DACs per channel. These DACs provide
levels for the driver, comparator, load currents, VHH buffer, OVD,
and clamp levels. There are three versions of output levels as
follows:
2.5 V to +7.5 V and tracks DUTGND. Controls the VH,
VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
3.0 V to +7.0 V and tracks DUTGND. Controls the
OVD levels.
2.5 V to +7.5 V and does not track DUTGND. Controls
the IOH and IOL levels.
There is one 16-bit DAC per channel. This DAC provides the
levels for the PMU. The output level is as follows:
2.5 V to +7.5 V and tracks DUTGND; controls the
PMU levels.
Table 32. Level Transfer Functions
DAC Transfer Function
Programmable Range1
(All 0s to All 1s)
Levels
VOUT = 2.0 × (VREF VREF_GND) × (Code/(214)) 0.5 × (VREF VREF_GND) + VDUTGND
Code = [VOUT VDUTGND + 0.5 × (VREF VREF_GND)] × [(214)/(2.0 × (VREF VREF_GND))]
2.5 V to +7.5 V
VH, VL, VT/VCOM,
VOL, VOH, VCH, VCL
VOUT = 4.0 × (VREF VREF_GND) × (Code/(214)) 1.0 × (VREF VREF_GND) + 2.0 + VDUTGND
Code = [VOUT VDUTGND 2.0 + 1.0 × (VREF VREF_GND)] × [(214)/(4.0 × (VREF VREF_GND))]
3.0 V to +17.0 V
VHH
VOUT = 2.0 × (VREF VREF_GND) × (Code/(214)) 0.6 × (VREF VREF_GND) + VDUTGND
Code = [VOUT VDUTGND + 0.6 × (VREF VREF_GND)] × [(214)/(2.0 × (VREF VREF_GND))]
3.0 V to +7.0 V
OVD
IOUT = [2.0 × (VREF VREF_GND) × (Code/(214)) 0.5 × (VREF VREF_GND)] × (0.012/5.0)
Code = [(IOUT × (5.0/0.012)) + 0.5 × (VREF VREF_GND)] × [(214)/(2.0 × (VREF VREF_GND))]
6 mA to +18 mA
IOH, IOL
VOUT = 2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) + VDUTGND
Code = [VOUT VDUTGND + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
2.5 V to +7.5 V
PMUDAC
IOUT = [2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) 2.5] × (0.050/5.0)
Code = [(IOUT × (5.0/0.050)) + 2.5 + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
50 mA to +50 mA
PMUDAC
(PMU FI Range A)
IOUT = [2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) 2.5] × (0.004/5.0)
Code = [(IOUT × (5.0/0.004)) + 2.5 + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
4 mA to +4 mA
PMUDAC
(PMU FI Range B)
IOUT = [2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) 2.5] × (0.0004/5.0)
Code = [(IOUT × (5.0/0.0004)) + 2.5 + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
400 μA to +400 μA
PMUDAC
(PMU FI Range C)
IOUT = [2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) 2.5] × (0.00004/5.0)
Code = [(IOUT × (5.0/0.00004)) + 2.5 + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
40 μA to +40 μA
PMUDAC
(PMU FI Range D)
IOUT = [2.0 × (VREF VREF_GND) × (Code/(216)) 0.5 × (VREF VREF_GND) 2.5] × (0.000004/5.0)
Code = [(IOUT × (5.0/0.000004)) + 2.5 + 0.5 × (VREF VREF_GND)] × [(216)/(2.0 × (VREF VREF_GND))]
4 μA to +4 μA
PMUDAC
(PMU FI Range E)
1 Programmable range includes a margin outside the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level
Transfer Function1
IOL
V(IOL)/5 V × 12 mA
IOH
V(IOH)/5 V × 12 mA
1 V(IOH)and V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode
Transfer Functions
Force Voltage
VOUT = PMUDAC
Measure Voltage
VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense)
Force Current
IOUT = [PMUDAC (VREF/2)]/(R1 × 5)
Measure Current
VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx × 5 × R1)
1 R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.
Table 35. PMU User Required Capacitors
Capacitor
Location
220 pF
Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A)
220 pF
Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A)
330 pF
Between GND and Pin B9 (SCAP0)
330 pF
Between GND and Pin B2 (SCAP1)
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