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| 型號： | ADATE207BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 標準包裝： | 1 |
| 類型： | 四針定時格式器 |
| PLL： | 是 |
| 主要目的： | 自動測試設(shè)備 |
| 電路數(shù)： | 4 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
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ADATE207
Rev. 0 | Page 13 of 36
2.5
2.0
1.5
1.0
0.5
0
70
10
20
30
40
50
60
TYPICAL VERNIER
05
55
7-
0
16
DELAY CODE
(n
s)
Figure 7. Delay Curve of a Typical Vernier
DRIVE AND COMPARE LOGIC
The drive logic consists of two high speed differential reset/set
flip flops controlling the drive data and drive enable signals.
They are controlled from the four events per channel, enabled
via decode of the event code. In addition, the flip flops can be
controlled from an adjacent channel event in a multiplex mode.
The four-channel device can be multiplexed such that there are
either four pins with four events each, or two pins with eight
events each.
The compare logic supports dual level comparators for voltage
comparisons against VOL and VOH levels. The comparator outputs
are checked against four possible states, low (less than VOL), high
(greater than VOH), off or midband (between VOL and VOH), and
valid (either above VOH or below VOL). The high comparator
inputs (COMP_H) are Logic 1 when the DUT output is greater
than VOH. The low comparator inputs (COMP_L) are Logic 1
when the DUT output is greater than VOL.
The compare logic supports both single edge and window com-
parisons and can support up to four comparisons per cycle using
the four events. Each comparison can generate a fail, accumulating
per pin with individual fail counters. Fail outputs are resynchro-
nized to T0 and output for fail processing.
Fails can be masked on a per edge basis and match mode is
supported. Masking of failures prevents incrementing of the fail
counter and the setting of the accumulated fail registers. It does
not prevent the fail signals from reflecting the comparison state
of the expect edge. Strobe comparison fails are associated with
the timing edge that generates the strobe.
A pair of timing edges can be used to create a window of time
over which to check the DUT output levels. Timing Edge D0
and Timing Edge D1 form a window with D0 opening the
window and D1 closing the window. Timing Edge D2 and
Timing Edge D3 are similarly employed for window
comparisons. Window comparison fails are associated with the
timing edge that generates the window close strobe. Window
failures only come out on D1 or D3 edges. Table 9 shows the
relationship between the edges on which the fails are detected
and the bit position on the PAT_FAIL pins.
Table 9. Edge and Window Fail Bit Descriptions
Bit
Fail1
Description
Fail
Mask Bit
3
PAT_FAIL_x[3]
Edge D3 Fail and Window
D2/D3 Fail
PAT_MASK[3]
2
PAT_FAIL_x[2]
Edge D2 Fail
PAT_MASK[2]
1
PAT_FAIL_x[1]
Edge D1 Fail and Window
D0/D1 Fail
PAT_MASK[1]
0
PAT_FAIL_x[0]
Edge D0 Fail
PAT_MASK[0]
1 PAT_FAIL_x refers to Channel 0 to Channel 3
.
PAT_MASK inputs mask failures across the channels for four
possible edges. Asserting PAT_MASK[0] masks failures for
Timing Edge D0. When failures are masked, the accumulated fail
register is not asserted, and the fail counts are not incremented. The
PAT_FAIL_x outputs remain asserted if the expected vector is
not seen allowing for match mode applications.
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