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參數(shù)資料
| 型號(hào)： | ADATE207BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 四針定時(shí)格式器 |
| PLL： | 是 |
| 主要目的： | 自動(dòng)測(cè)試設(shè)備 |
| 電路數(shù)： | 4 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
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ADATE207
Rev. 0 | Page 7 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADATE207
PATTERN DATA
PERIOD DATA
COMPARE FAILS
RECEIVE DATA
CH3 DCL I/F
CH2 DCL I/F
CH1 DCL I/F
CH0 DCL I/F
COMMAND/
STATUS BUS
TIME
MEASUREMENT
05
55
7-
0
09
Figure 5. Connection Overview Diagram
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
BOTTOM
VIEW
(Not to Scale)
ADATE207
05
55
7-
0
14
Figure 6. Ball Grid Array
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Input/Output1
Type
Description
B4, A4, C5, D6
PAT_MASK[3:0]
I
LVCMOS25
Mask Failures. Used to mask failures on D3,
D2, D1 and D0 edges, respectively. Clocked
by MCLK.
T3, U1, U2, T4, U3, V4, U5, W4
PAT_PATDATA_0[7:0]
I
LVCMOS25
Channel 0 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 0. Clocked by MCLK.
B5, A5, C6, B6, A6, C7, B7, D8
PAT_PATDATA_1[7:0]
I
LVCMOS25
Channel 1 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 1. Clocked by MCLK.
W212, V12, Y13, U12, W13,
V13, Y14, W14
PAT_PATDATA_2[7:0]
I
LVCMOS25
Channel 2 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 2. Clocked by MCLK.
A16, B16, D15, C16, A17,
B17, D16, C17
PAT_PATDATA_3[7:0]
I
LVCMOS25
Channel 3 Waveform Memory Address. Use
these pins to address waveform memory for
Channel 3. Clocked by MCLK.
Y4, W5, V6
PAT_FAIL_0[3:0]
O
LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 0.
Clocked by MCLK.
B8, A8, B9, B10
PAT_FAIL_1[3:0]
O
LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 1.
Clocked by MCLK.
V8, W8, W9, Y9
PAT_FAIL_2[3:0]
O
LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 2.
Clocked by MCLK.
B12, C12, B13, A14
PAT_FAIL_3[3:0]
O
LVCMOS25
Fails on D3, D2, D1 and D0 Edges for Channel 3.
Clocked by MCLK.
W6, Y6, W7, Y7
PAT_DUTDATA_0[3:0]
O
LVCMOS25
DUT Capture Data from Channel 0. Clocked
by MCLK.
C10, A11, B11, A12
PAT_DUTDATA_1[3:0]
O
LVCMOS25
DUT Capture Data from Channel 1. Clocked
by MCLK.
V10, W10, Y10, W11
PAT_DUTDATA_2[3:0]
O
LVCMOS25
DUT Capture Data from Channel 2. Clocked
by MCLK.
B14, C14, A15, B15
PAT_DUTDATA_3[3:0]
O
LVCMOS25
DUT Capture Data from Channel 3. Clocked
by MCLK.
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