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參數(shù)資料
| 型號(hào)： | ADATE207BBPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING FORMATTER QUAD 256BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 四針定時(shí)格式器 |
| PLL： | 是 |
| 主要目的： | 自動(dòng)測(cè)試設(shè)備 |
| 電路數(shù)： | 4 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
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ADATE207
Rev. 0 | Page 26 of 36
Name:
Waveform D1 Vernier Delay and Action
Address:
0x08
Type:
Read/Write
Table 22. Waveform D1 Vernier Delay and Action
Position
Description
Reset State
Bits[15:10]
D1 Vernier Delay. The vernier delay is represented in binary by the equation, vvvvvv × (2.5 ns/64).
Undefined
Bits[09:04]
Not Used.
0x00
Bits[03:00]
D1 Action. A binary encoded data field.
Undefined
0x0 = no action.
0x1 = drive low.
0x2 = drive high.
0x3 = force off.
0x4 = force on.
0x5 = force down.
0x6 = force up.
0x7 = edge compare low.
0x8 = edge compare high.
0x9 = edge compare off.
0xA = edge compare valid.
0xF = close window/compare unknown.
Name:
Waveform D1Course Delay
Address:
0x09
Type:
Read/Write
Table 23. Waveform D1 Course Delay
Position
Description
Reset State
Bits[15:00]
D1 Course Delay. Number of 2.5 ns clock periods to count.
Undefined
When this count is completed, add the vernier delay (defined by the D1 vernier value programmed
into the waveform D1 vernier delay and action register) to the D1 course delay to place an edge in
time.
Waveform D1 vernier delay and action must be written immediately before this register for the
waveform memory to be correctly written.
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