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參數(shù)資料
| 型號(hào)： | ADADC71KD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT HIGH RES 32-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 850mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-CDIP（0.900"，22.86mm） |
| 供應(yīng)商設(shè)備封裝： | 32-CDIP 底部銅焊 |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極 |
ADADC71
Rev. C | Page 6 of 12
THEORY OF OPERATION
The analog continuum is partitioned into 216 discrete ranges for
16-bit conversion. All analog values within a given quantum are
represented by the same digital code, usually assigned to the
nominal midrange value. An inherent quantization uncertainty
of ±1/2 LSB is associated with the resolution, in addition to the
actual conversion errors.
0.016
0.013
0.0195
0.0150
0.0180
0
–0.0150
–0.0180
–0.0195
0.006
0.003
0
–0.003
–0.006
–0.016
–0.013
025
70
03537-002
TEMPERATURE (
°C)
LINEARITY
ERRO
R
(%
FSR)
ADADC71
±3ppm/°C,
±0.006%, @ 25°C
Figure 2. Linearity Error vs. Temperature
0.100
0.038
–0.038
0
–0.068
0.068
0
–0.100
0
60
50
40
30
20
10
03537-003
TEMPERATURE (
°C)
G
A
IN
DRIFT
ERRO
R
(%
FSR)
70
±15ppm/°C
Figure 3. Gain Drift Error vs. Temperature
The actual conversion errors associated with ADCs are
combinations of analog errors due to the linear circuitry,
matching and tracking properties of the ladder and scaling
networks, reference error, and power supply rejection. The
matching and tracking errors in the converter have been
minimized by the use of monolithic DACs that include the
scaling network. The initial gain and offset errors are specified
at ±0.2% FSR for gain and ±0.1% FSR for offset. These errors
may be trimmed to 0 by using external trim circuits as shown in
ranges as the deviation from a true straight-line transfer
characteristic from a zero voltage analog input, which calls for a
zero digital output, to a point that is defined as a full scale. The
linearity error is based on the DAC resistor ratios. It is
unadjustable and is the most meaningful indication of ADC
accuracy. Differential nonlinearity is a measure of the deviation
in the staircase step width between codes from the ideal least
significant bit step size (Figure 4).
03537-004
000 ... 000
ALL BITS ON
GAIN
ERROR
OFFSET
ERROR
ALL BITS OFF
–1/2LSB
+1/2LSB
011 ... 111
111 ... 111
DIGITAL
OUTPUT
(
C
OB
CODE)
–FS
ANALOG INPUT
0
+FSR – 1LSB
Figure 4. Transfer Characteristics for an Ideal Bipolar ADC
Monotonic behavior requires that the differential linearity error
be less than 1 LSB. However, a monotonic converter can have
missing codes. The ADADC71 is specified as having no missing
codes over temperature ranges noted in the Specifications
section.
There are three types of drift error over temperature: offset, gain
and linearity. Offset drift causes a shift of the transfer
characteristic left or right on the diagram over the operating
temperature range. Gain drift causes a rotation of the transfer
characteristic about the zero point for unipolar ranges or the
negative full-scale point for bipolar ranges. The worst case
accuracy drift is the summation of all three drift errors over
temperature. Statistically, however, the drift error behaves as the
root-sum-square (RSS) and can be shown as
2
L
O
G
RSS
∈
+
∈
+
∈
=
where:
).
/
(
C
ppm
error
drift
gain
G
°
=
∈
).
/
(
C
FSR
of
ppm
error
drift
offset
O
°
=
∈
).
/
(
C
FSR
of
ppm
error
linearity
L
°
=
∈
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