參數資料
| 型號： | ADADC71KD |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT HIGH RES 32-CDIP |
| 標準包裝： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 20k |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 850mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-CDIP（0.900"，22.86mm） |
| 供應商設備封裝： | 32-CDIP 底部銅焊 |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，單極；2 個單端，雙極 |
ADADC71
Rev. C | Page 9 of 12
Table 6. Input Voltage Range and LSB Values
Analog Input Voltage Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
Code Designation
CSB3
One Least Significant Bit (LSB)
n
2
FSR
n
2
V
20
n
2
V
10
n
2
V
5
n
2
V
10
n
2
V
5
n = 8
78.13 mV
39.06 mV
19.53 mV
39.06 mV
19.53 mV
n = 10
19.53 mV
9.77 mV
4.88 mV
9.77 mV
4.88 mV
n = 12
4.88 mV
2.44 mV
1.22 mV
2.44 mV
1.22 mV
n = 13
2.44 mV
1.22 mV
0.61 mV
1.22 mV
0.61 mV
n = 14
1.22 mV
0.61 mV
0.31 mV
0.61 mV
0.31 mV
n = 15
0.61 mV
0.31 mV
0.15 mV
0.31 mV
0.15 mV
1 COB = complementary offset binary.
2 CTC = complementary twos complement—achieved by using an inverter to complement the most significant bit to produce (MSB).
3 CSB = complementary straight binary.
03537-
011
–15V
+15V
A
16-BIT SUCCESSIVE
APPROMIXATION REGISTER
16-BIT DAC
REF
CONTROL
3.
75k
Ω
3.
75k
Ω
24
26
19
29
28
22
21
25
eIN
(0V TO +10V)
IIN
KEEP/
REJECT
7.5k
Ω
+15V
–15V
ZERO
ADJ
10k
Ω
TO
100k
Ω
27
IOS = 1.3mA
ADADC71
1.8M
Ω
1
μF
+5V
+
30
+
1
μF
+
1
μF
+15V
–15V
GAIN
ADJ
10k
Ω
TO
100k
Ω
270k
Ω
0.01
μF
NOTE:
ANALOG (
) AND DIGITAL (
) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY.
23
Figure 11. Analog and Power Connections
for Unipolar 0 V to +10 V Input Range
03537-
012
–15V
+15V
A
16-BIT SUCCESSIVE
APPROMIXATION REGISTER
16-BIT DAC
REF
CONTROL
3.
75k
Ω
3.
75k
Ω
24
26
19
29
28
22
21
25
eIN
(–10V TO +10V)
IIN
KEEP/
REJECT
7.5k
Ω
+15V
–15V
ZERO
ADJ
10k
Ω
TO
100k
Ω
27
IOS = 1.3mA
ADADC71
1.8M
Ω
1
μF
+5V
+
30
+
1
μF
+
1
μF
+15V
–15V
GAIN
ADJ
10k
Ω
TO
100k
Ω
270k
Ω
0.01
μF
NOTE:
ANALOG (
) AND DIGITAL (
) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY.
23
Figure 12. Analog and Power Connections
for Bipolar 10 V to +10 V Input Range
CALIBRATION (14-BIT RESOLUTION EXAMPLES)
External zero adjustment and gain adjustment potentiometers,
device calibration. To prevent interaction of these two
adjustments, zero is always adjusted first and then gain. Zero is
adjusted with the analog input near the most negative end of the
analog range (0 for unipolar and FS for bipolar input ranges).
Gain is adjusted with the analog input near the most positive
end of the analog range.
0 V to +10 V Range
Set the analog input to +1 LSB14 = 0.00061 V. Adjust zero for
digital output = 11111111111110. Zero is now calibrated. Set
analog input to +FSR 2 LSB = +9.9987 V. Adjust gain for
00000000000001 digital output code; full-scale (gain) is now
calibrated. Half-scale calibration check: set analog input to
+5.00000 V; digital output code should be 01111111111111.
10 V to +10 V Range
Set the analog input to 9.99878 V; adjust zero for
11111111111110 digital output (complementary offset binary)
code. Set analog input to 9.99756 V; adjust gain for
00000000000001 digital output (complementary offset binary)
code. Half-scale calibration check: set analog input to 0.00000
V; digital output (complementary offset binary) code should be
01111111111111.
Other Ranges
Representative digital coding for 0 to +10 V and 10 V to +10 V
ranges is given above. Coding relationships and calibration
points for 0 to +5 V, 2.5 V to +2.5 V and 5 V to +5 V ranges
can be found by proportionally halving the corresponding code
equivalents listed for the 0 to +10 V and 10 V to +10 V ranges,
respectively, as indicated in Table 5.
Zero and full-scale calibration can be accomplished to a
precision of approximately ±1/2 LSB using the static adjustment
procedure described above. By summing a small sine or
triangular wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end point) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented
in A/D Conversion Handbook, D. Sheingold, Analog Devices,
Inc., 1986 Part II, Chapter 4.
相關PDF資料 |
PDF描述 |
|---|---|
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
| ADC0820CCM+ | IC ADC 8-BIT HS 20-SOIC |
| ADF4001BRU | IC CLOCK GEN PLL 16-TSSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADADC71KM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| ADADC72 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete, High Resolution 16-Bit A/D Converters |
| ADADC72AD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog-to-Digital Converter， 16-Bit |
| ADADC72AM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
| ADADC72BD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog-to-Digital Converter， 16-Bit |
發(fā)布緊急采購，3分鐘左右您將得到回復。