參數(shù)資料
型號(hào)： ADADC71KD
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/12頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT HIGH RES 32-CDIP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
采樣率（每秒）： 20k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 850mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 通孔
封裝/外殼： 32-CDIP（0.900"，22.86mm）
供應(yīng)商設(shè)備封裝： 32-CDIP 底部銅焊
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；2 個(gè)單端，雙極
ADADC71
Rev. C | Page 8 of 12
DIGITAL OUTPUT DATA
Parallel data from TTL storage registers is in negative true form
(Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding
is complementary binary for unipolar ranges and comple-
mentary offset binary for bipolar ranges. Parallel data becomes
valid at least 20 ns before the STATUS flag returns to Logic 0,
permitting parallel data transfer to be clocked on the 1 to 0
transition of the STATUS flag (see Figure 9). Parallel data
outputs change state on positive-going clock edges.
03537-009
BIT 16
VALID
BUSY
(STATUS)
20ns MIN TO 90ns
Figure 9. LSB Valid to Status Low
Short Cycle Input:
Pin 32 (SHORT CYCLE) permits the timing
cycle shown in Figure 8 to be terminated after any number of
desired bits has been converted, allowing somewhat shorter
conversion times in applications not requiring full 16-bit
resolution. When 10-bit resolution is desired, Pin 32 is
connected to Bit 11 output Pin 11. The conversion cycle then
terminates and the STATUS flag resets after the Bit 10 decision
(t10 + 40 ns in the timing diagram of Figure 8). Short cycle
connections and associated maximum 8-, 10-, 12-, 13-, 14-, and
15-bit conversion times are summarized in Table 3.
Table 3. Short Cycle Connections
Resolution
Connect Short
Cycle Pin 32
to
Bits
% FSR
Maximum
Conversion
Time
Status
Flag
Reset
N/C (Open)
16
0.0015
57.0
t16 + 40 ns
Pin 16
15
0.003
53.5
t15 + 40 ns
Pin 15
14
0.006
50.0
t14 + 40 ns
Pin 14
13
0.012
46.5
t13 + 40 ns
Pin 13
12
0.024
42.8
t12 + 40 ns
Pin 11
10
0.100
35.6
t10 + 40 ns
Pin 9
8
0.390
28.5
t8 + 40 ns
INPUT SCALING
The ADADC71 inputs should be scaled as close to the
maximum input signal range as possible in order to utilize the
maximum signal resolution of the ADC. Connect the input
signal as shown in Table 4. See Figure 10 for circuit details.
03537-010
22
ANALOG
COMMON
26
BIPOLAR
OFFSET
COMP IN
24
25
27
7.5k
Ω
R2
3.75k
Ω
10V SPAN
20V SPAN
R1
3.75k
Ω
FROM DAC
COMPARATOR
TO
SAR
VREF
Figure 10. ADADC71 Input Scaling Circuit
Table 4. Input Scaling Connections
Input Signal Line
Output Code
Connect Pin 26 to
Connect Pin 24 to
For Direct Input,
Connect Input Signal to
±10 V
COB
Pin 271
Input Signal
Pin 24
±5 V
COB
Pin 271
Open
Pin 25
±2.5 V
COB
Pin 271
Pin 271
Pin 25
0 V to +5 V
CSB
Pin 22
Pin 271
Pin 25
0 V to +10 V
CSB
Pin 22
Open
Pin 25
0 V to +20 V
CSB
Pin 22
Input Signal
Pin 24
1 Pin 27 is extremely sensitive to noise and should be guarded by analog common
Table 5. Transition Values vs. Calibration Codes
Output Code
MSB
LSB1
Range
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
000. . . .0002
+Full Scale
+10 V
+5 V
+2.5 V
+10 V
+5 V
3/2 LSB
011 . . . 111
Mid Scale
0
+5 V
+2.5 V
1/2 LSB
111 . . . 110
Full Scale
10 V
5 V
2.5 V
0 V
+1/2 LSB
1 For LSB value for range and resolution used, see Table 6.
2 Voltages given are the nominal value for transition to the code specified.
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