參數(shù)資料
型號: ADADC71KD
廠商: Analog Devices Inc
文件頁數(shù): 7/12頁
文件大小: 0K
描述: IC ADC 16BIT HIGH RES 32-CDIP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 20k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 850mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 32-CDIP(0.900",22.86mm)
供應(yīng)商設(shè)備封裝: 32-CDIP 底部銅焊
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極
ADADC71
Rev. C | Page 4 of 12
Parameter
Min
Typ
Max
Units
Comment
DIGITAL OUTPUT1
All codes complementary
Parallel Output Codes6
Unipolar
CSB
Bipolar
COB, CTC7
Output Drive
5
LSTTL Loads
Status
Logic 1 during conversion
Status Output Drive
5
LSTTL Loads
Internal Clock
Clock Output Drive
5
LSTTL Loads
Frequency
400
kHz
INTERNAL REFERENCE VOLTAGE
6.3
V dc
Error
±5
%
Max External Current Drain with No
Degradation of Specifications
±200
μA
Temperature Coefficient
±10
ppm/oC
POWER SUPPLY REQUIREMENTS
Power Consumption
645
850
mW
Rated Voltage, Analog
±15
±0.5
V dc
Rated Voltage, Digital
±5
±0.25
V dc
Supply Drain +15 V dc
+16
mA
Supply Drain 15 V dc
21
mA
Supply Drain +5 V dc
+18
mA
TEMPERATURE RANGE
Specification
0 to +70
°C
Operating (Derated Specs)
25 to +85
°C
Storage
55 to +125
°C
1 For inputs Logic 0 = 0.8 V, max. Logic 1 = 2.0 V, min. For digital outputs Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.
2 Adjustable to 0.
3 Full scale range.
4 For definition of “No Missing Codes,” refer to the Theory of Operation section.
5 Conversion time may be shortened with short cycle set for lower resolution.
6 CSB—Complementary straight binary. COB— Complementary offset binary, CTC—Complementary twos complement.
7 CTC coding obtained by inverting MSB (Pin 1).
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