參數(shù)資料
型號(hào)： AD9985BSTZ-110
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁數(shù)： 23/32頁
文件大?。?/td> 349K
代理商： AD9985BSTZ-110
AD9985
10
Rev. 0 | Page 23 of 32
2
This bit determines whether the Red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr
(or YUV), the Y channel is referenced to ground, but
the CbCr channels are referenced to midscale.
Clamping to midscale actually clamps to Pin 37.
Table 28. Red Clamp Select Settings
Clamp
Function
0
Clamp to Ground
1
Clamp to Midscale (Pin 37)
Red Clamp Select
The default setting for this register is 0.
10
1
This bit determines whether the Green channel is
clamped to ground or to midscale.
Table 29. Green Clamp Select Settings
Clamp
Function
0
Clamp to Ground
1
Clamp to Midscale (Pin 37)
Green Clamp Select
The default setting for this register is 0.
10
0
This bit determines whether the Blue channel is
clamped to ground or to midscale.
Table 30. Blue Clamp Select Settings
Clamp
Function
0
Clamp to Ground
1
Clamp to Midscale (Pin 37)
Blue Clamp Select
The default for this register is 0.
11
7–0
This register is used to set the responsiveness of the
sync separator. It sets how many internal 5 MHz clock
periods the sync separator must count to before
toggling high or low. It works like a low-pass filter to
ignore Hsync pulses in order to extract the Vsync
signal. This register should be set to some number
greater than the maximum Hsync pulsewidth. Note
that the sync separator threshold uses an internal
dedicated clock with a frequency of approximately
5 MHz.
Sync Separator Threshold
The default for this register is 32.
12
7–0 Pre-Coast
This register allows the coast signal to be applied prior
to the Vsync signal. This is necessary in cases where
pre-equalization pulses are present. The step size for
this control is one Hsync period.
The default is 0.
13
7–0
This register allows the coast signal to be applied
following the Vsync signal. This is necessary in cases
where post-equalization pulses are present. The step
size for this control is one Hsync period.
Post-Coast
The default is 0.
14
7
This bit is used to indicate when activity is detected on
the Hsync input pin (Pin 30). If Hsync is held high or
low, activity will not be detected.
Table 31. Hsync Detection Results
Detect
Function
0
No Activity Detected
1
Activity Detected
Hsync Detect
The Sync Processing Block Diagram (Figure 14) shows
where this function is implemented.
14
6
This bit indicates which Hsync input source is being
used by the PLL (Hsync input or Sync-on-Green).
Bits 7 and 1 in this register determine which source is
used. If both Hsync and SOG are detected, the user
can determine which has priority via Bit 3 in
Register 0EH. The user can override this function via
Bit 4 in Register 0EH. If the override bit is set to
Logic 1, this bit will be forced to whatever the state of
Bit 3 in Register 0EH is set to.
Table 32. Active Hsync Results
Bit 7
Bit 1
Bit 4,
(Hsync
(SOG
Reg 0EH
Detect)
Detect)
(Override)
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
AHS – Active Hsync
AHS
Bit 3 in 0EH
1
0
Bit 3 in 0EH
Bit 3 in 0EH
AHS = 0 means use the Hsync pin input for Hsync.
AHS = 1 means use the SOG pin input for Hsync.
The override bit is in Register 0EH, Bit 4.
14
5
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the
polarity of the Hsync input. The detection circuit’s
location is shown in the Sync Processing Block
Diagram (Figure 14).
Detected Hsync Input Polarity Status
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