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參數(shù)資料
| 型號： | AD9985BSTZ-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 349K |
| 代理商： | AD9985BSTZ-110 |
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AD9985
disappear. In other systems, such as those that employ
Composite Sync (Csync) signals or embedded Sync-on-Green
(SOG), Hsync includes equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it will attempt to lock to this
new frequency, and will have changed frequency by the end of
Rev. 0 | Page 16 of 32
the Vsync period. It will then take a few lines of correct Hsync
timing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
.
P0
P1
P2
P3
P4
P5
P6
P7
5-PIPE DELAY
D0
D1
D2
D3
D4
D5
D6
D7
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
VARIABLE DURATION
0
Figure 10. 4:4:4 Mode (For RGB and YUV)
P0
P1
P2
P3
P4
P5
P6
P7
5-PIPE DELAY
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
G
OUTA
HSOUT
U0
V1
U2
V3
U4
V5
U6
V7
R
OUTA
VARIABLE DURATION
0
Figure 11. 4:2:2 Mode (For YUV Only)
2-WIRE SERIAL REGISTER MAP
The AD9985 is initialized and controlled by a set of registers, that determine the operating modes. An external controller is employed to
write and read the control registers through the two-line serial interface port.
Table 10. Control Register Map
Write and
Read or
Read Only
Bits
Value
Register Name
Function
00H
RO
7:0
Chip Revision
An 8-bit register that represents the silicon revision level.
01H*
R/W
7:0
01101001
PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Greater values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
02H*
R/W
7:4
1101****
PLL Div LSB
Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider
word.
Hex
Address
Default
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| AD9985KST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
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| AD9985KSTZ-140 | 功能描述:IC INTERFACE 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD9990 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel, 14-Bit CCD Signal Processor with V-Driver and Precision Timing |
| AD9990BBCZ | 功能描述:IC CCD SGNL PROCESSOR 112CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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