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| 型號： | AD9985BSTZ-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 349K |
| 代理商： | AD9985BSTZ-110 |
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AD9985
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Rev. 0 | Page 15 of 32
PLL
Div
799
835
841
831
1025
1055
1039
1055
1047
1343
1327
1313
1335
1383
1687
1687
AD9985KSTZ
AD9985BSTZ
Standard
Modes
VGA
SVGA
XGA
SXGA
TV Modes
480i
480p
720p
1080i
TIMING
The following timing diagrams show the operation of the
AD9985.
Resolution
640 × 480
800 × 600
1024 × 768
1280 × 1024
720 × 480
720 × 483
1280 × 720
1920 × 1080
Refresh
Rate (Hz)
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
60
60
60
60
Horizontal
Frequency (kHz)
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
15.75
31.47
45.0
33.75
Pixel Rate
(MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
13.51
27.00
74.25
74.25
VCORNGE
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
11
Current
110
110
110
100
100
100
101
101
101
101
100
100
101
101
110
110
VCORNGE
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
Current
011
010
010
010
010
011
100
100
101
011
011
011
100
100
101
857
857
1649
2199
00
00
10
10
011
110
100
100
00
00
10
10
011
011
011
011
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
There is a pipeline in the AD9985, which must be flushed before
valid data becomes available. This means that four data sets are
presented before valid data is available.
t
PER
t
CYCLE
t
SKEW
DATACK
DATA
HSOUT
0
Figure 9. Output Timing
HSYNC TIMING
Horizontal Sync (Hsync) is processed in the AD9985 to
eliminate ambiguity in the timing of the leading edge with
respect to the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to Hsync, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9985. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be
programmed either active high or active low (Register 0EH,
Bit 5). Second, HSOUT is aligned with DATACK and data
outputs. Third, the duration of HSOUT (in pixel clocks) is set
via Register 07H. HSOUT is the sync signal that should be used
to drive the rest of the display system.
COAST TIMING
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary and should not be used, and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the
Vertical Sync period (Vsync). In some cases, Hsync pulses
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