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參數(shù)資料
| 型號： | AD9985KSTZ-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 349K |
| 代理商： | AD9985KSTZ-140 |
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110 MSPS/140 MSPS Analog Interface for
Flat Panel Displays
AD9985
FEATURES
Rev.
0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
Automated clamping level adjustment 140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
R
AIN
R
OUTA
G
AIN
G
OUTA
B
AIN
B
OUTA
MIDSCV
SYNC
PROCESSING
AND CLOCK
GENERATION
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
SERIAL REGISTER AND
POWER MANAGEMENT
SCL
SDA
A0
SOGIN
FILT
CLAMP
COAST
HSYNC
AD9985
CLAMP
8
A/D
CLAMP
8
A/D
CLAMP
8
A/D
0
AUTO CLAMP
LEVEL ADJUST
AUTO CLAMP
LEVEL ADJUST
AUTO CLAMP
LEVEL ADJUST
Figure 1.
GENERAL DESCRIPTION
The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985 includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.
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