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參數資料
| 型號： | AD9959BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 44/44頁 |
| 文件大小： | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9959
Rev. B | Page 9 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1
SYNC_IN
2
SYNC_OUT
3
MASTER_RESET
4
PWR_DWN_CTL
5
AVDD
6
AGND
7
AVDD
8
CH2_IOUT
9
CH2_IOUT
10
AGND
11
AVDD
12
AGND
13
CH3_IOUT
14
CH3_IOUT
35
CH1_IOUT
36
CH1_IOUT
37
AVDD
38
AGND
39
AVDD
40
P0
41
P1
42
P2
34
AGND
33
AVDD
32
AGND
31
AVDD
30
CH0_IOUT
29
CH0_IOUT
15
A
V
D
16
A
G
N
D
17
D
A
C
_R
S
E
T
19
A
V
D
21
A
V
D
20
A
G
N
D
22
R
E
F
_C
L
K
23
R
E
F
_C
L
K
24
C
L
K
_M
O
D
E
_S
E
L
25
A
G
N
D
26
A
V
D
27
L
O
P
_F
IL
T
E
R
28
A
G
N
D
18
A
G
N
D
45
D
V
D
46
I/
O
_U
P
D
A
T
E
47
C
S
48
S
C
L
K
49
D
V
D
_I
/O
50
S
D
IO
_0
51
S
D
IO
_1
52
S
D
IO
_2
53
S
D
IO
_3
54
S
Y
N
C
_C
L
K
44
D
G
N
D
43
P
3
TOP VIEW
(Not to Scale)
AD9959
55
D
V
D
56
D
G
N
D
05
24
6-
0
03
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC_IN
I
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_OUT pin of
the master AD9959 device.
2
SYNC_OUT
O
Used to Synchronize Multiple AD9959 Devices. Connects to the SYNC_IN pin of the
slave AD9959 devices.
3
MASTER_RESET
I
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9959 internal
registers to their default state, as described in the Register Maps and Bit Descriptions
section.
4
PWR_DWN_CTL
I
External Power-Down Control.
5, 7, 11, 15, 19, 21,
26, 31, 33, 37, 39
AVDD
I
Analog Power Supply Pins (1.8 V).
6, 10, 12, 16, 18, 20,
25, 28, 32, 34, 38
AGND
I
Analog Ground Pins.
45, 55
DVDD
I
Digital Power Supply Pins (1.8 V).
44, 56
DGND
I
Digital Power Ground Pins.
8
CH2_IOUT
O
True DAC Output. Terminates into AVDD.
9
CH2_IOUT
O
Complementary DAC Output. Terminates into AVDD.
13
CH3_IOUT
O
True DAC Output. Terminates into AVDD.
14
CH3_IOUT
O
Complementary DAC Output. Terminates into AVDD.
17
DAC_RSET
I
Establishes the Reference Current for All DACs. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
22
REF_CLK
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated
in single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
23
REF_CLK
I
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended
mode, this is the input. See the Modes of Operation section for the reference clock
configuration.
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| AD9959BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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