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| 型號： | AD9959BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS QUAD 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9959
Rev. B | Page 23 of 44
Eight-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 10 (eight-level).
The AFP select bits (CFR[23:22]) are set to a nonzero value.
The RU/RD bits (FR1[11:10]) and the linear sweep enable bit
(CFR[14]) are disabled. Note that the AFP select bits of the
three channels not being used must be set to 00. Table 11 shows
the assignment of profile pins and channels.
For the condition in Table 11, the choice of channel word registers
is based on the 3-bit value presented to Profile Pins [P0:P2]. For
example, if PPC = X10 and [P0:P2] = 111, the contents of the
Channel Word 7 register of Channel 2 are presented to the output
of Channel 2.
16-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 11 (16-level). The
AFP select bits (CFR[23:22]) are set to the desired modulation
type. The RU/RD bits (FR1[11:10]) and the linear sweep enable
bit (CFR[14]) are disabled. The AFP select bits of the three
channels not being used must be set to 00. Table 12 displays how
the profile pins and channels are assigned.
For the conditions in Table 12, the profile register chosen is
based on the 4-bit value presented to Profile Pins [P0:P3].
For example, if PPC = X11 and [P0:P3] = 1110, the contents of
the Channel Word 14 register of Channel 3 is presented to the
output of Channel 3.
Two-Level Modulation Using Profile Pins for RU/RD
When the RU/RD bits = 01, Profile Pin P2 and Profile Pin P3
are available for RU/RD. Note that only a modulation level of
two is available in this mode. See Table 13 for available pin
assignments.
Eight-Level Modulation Using a Profile Pin for RU/RD
When the RU/RD bits = 10, Profile Pin P3 is available for RU/RD.
Note that only a modulation level of eight is available in this
mode. See Table 14 for available pin assignments.
Table 11. Profile Pin and Channel Assignments for Eight-Level Modulation (No RU/RD)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X00
CH0
X
Eight-level modulation on CH0, no RU/RD
X01
CH1
X
Eight-level modulation on CH1, no RU/RD
X10
CH2
X
Eight-level modulation on CH2, no RU/RD
X11
CH3
X
Eight-level modulation on CH3, no RU/RD
Table 12. Profile Pin and Channel Assignments for 16-Level Modulation (No RU/RD)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X00
CH0
16-level modulation on CH0, no RU/RD
X01
CH1
16-level modulation on CH1, no RU/RD
X10
CH2
16-level modulation on CH2, no RU/RD
X11
CH3
16-level modulation on CH3, no RU/RD
Table 13. Profile Pin and Channel Assignments for Two-Level Modulation (RU/RD Enabled)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
000
CH0
CH1
CH0 RU/RD
CH1 RU/RD
Two-level modulation on CH0 and CH1 with RU/RD
001
CH0
CH2
CH0 RU/RD
CH2 RU/RD
Two-level modulation on CH0 and CH2 with RU/RD
010
CH0
CH3
CH0 RU/RD
CH3 RU/RD
Two-level modulation on CH0 and CH3 with RU/RD
011
CH1
CH2
CH1 RU/RD
CH2 RU/RD
Two-level modulation on CH1 and CH2 with RU/RD
100
CH1
CH3
CH1 RU/RD
CH3 RU/RD
Two-level modulation on CH1 and CH3 with RU/RD
101
CH2
CH3
CH2 RU/RD
CH3 RU/RD
Two-level modulation on CH2 and CH3 with RU/RD
Table 14. Profile Pin and Channel Assignments for Eight-Level Modulation (RU/RD Enabled)
Profile Pin Config. (PPC)
(FR1[14:12])
P0
P1
P2
P3
Description
X00
CH0
CH0 RU/RD
Eight-level modulation on CH0 with RU/RD
X01
CH1
CH1 RU/RD
Eight-level modulation on CH1 with RU/RD
X10
CH2
CH2 RU/RD
Eight-level modulation on CH2 with RU/RD
X11
CH3
CH3 RU/RD
Eight-level modulation on CH3 with RU/RD
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