參數(shù)資料
型號： AD9958/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 42/44頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9958
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9958 Eval Brd BOM
標準包裝： 1
系列： AgileRF™
主要目的： 計時，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9958
主要屬性： 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 500MHz 2 通道圖形用戶界面
已供物品： 板，線纜，軟件
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9958BCPZ-REEL7-ND - IC DDS DUAL 10BIT DAC 56LFCSP
AD9958BCPZ-ND - IC DDS DUAL 500MSPS DAC 56LFCSP
Data Sheet
AD9958
Rev. B | Page 7 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Total Power Dissipation—Both Channels On, Single-
Tone Mode
315
380
mW
Dominated by supply variation
Total Power Dissipation—Both Channels On, with
Sweep Accumulator
350
420
mW
Dominated by supply variation
Total Power Dissipation—Full Power-Down
13
mW
IAVDD—Both Channels On, Single-Tone Mode
90
105
mA
IAVDD—Both Channels On, Sweep Accumulator,
REFCLK Multiplier, and 10-Bit Output Scalar
Enabled
95
110
mA
IDVDD—Both Channels On, Single-Tone Mode
60
70
mA
IDVDD—Both Channels On, Sweep Accumulator,
REFCLK Multiplier, and 10-Bit Output Scalar
Enabled
70
80
mA
IDVDD_I/O
22
mA
IDVDD = read
30
mA
IDVDD = write
IAVDD Power-Down Mode
2.5
mA
IDVDD Power-Down Mode
2.5
mA
DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE2, 3
Frequency, Phase, and Amplitude Words to DAC
Output with Matched Latency Enabled
29
SYSCLKs
Frequency Word to DAC Output with Matched
Latency Disabled
29
SYSCLKs
Phase Offset Word to DAC Output with Matched
Latency Disabled
25
SYSCLKs
Amplitude Word to DAC Output with Matched
Latency Disabled
17
SYSCLKs
DATA LATENCY (PIPELINE DELAY) MODULATION MODE3, 4
Frequency Word to DAC Output
34
SYSCLKs
Phase Offset Word to DAC Output
29
SYSCLKs
Amplitude Word to DAC Output
21
SYSCLKs
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE3,4
Frequency Rising/Falling Delta-Tuning Word to DAC
Output
41
SYSCLKs
Phase Offset Rising/Falling Delta-Tuning Word to
DAC Output
37
SYSCLKs
Amplitude Rising/Falling Delta-Tuning Word to DAC
Output
29
SYSCLKs
1
For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.
2
Data latency is referenced to I/O_UPDATE.
3
Data latency is fixed.
4
Data latency is referenced to a profile change.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9959 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs
AD9959/PCBZ 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9959/PCBZ 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B
AD9959/PCBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs
AD9959_08 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs
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