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參數(shù)資料
| 型號： | AD9957BSVZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/64頁 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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Data Sheet
AD9957
Rev. C | Page 11 of 64
Pin No.
Mnemonic
I/O1
Description
59
I/O_UPDATE
I/O
Input/Output Update; Digital Input Or Output (Active High) Depending on the Internal I/O
Update Active Bit. A high on this pin indicates a transfer of the contents of the I/O buffers
to the corresponding internal registers.
60
OSK
I
Output Shift Keying, Digital Input (Active High). When using OSK (manual or automatic),
this pin controls the OSK function. See the Output Shift Keying (OSK) section of the data
sheet for details. When not using OSK, tie this pin high.
67
SDIO
I/O
Serial Data Input/Output, Digital Input/Output (Active High). This pin can be either
unidirectional or bidirectional (default), depending on configuration settings. In
bidirectional serial port mode, this pin acts as the serial data input and output. In
unidirectional, it is an input only.
68
SDO
O
Serial Data Output, Digital Output (Active High). This pin is only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is
not operational and should be left floating.
69
SCLK
I
Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin
provides the serial data clock for the control data path. Write operations to the AD9957
use the rising edge. Readback operations from the AD9957 use the falling edge.
70
CS
I
Chip Select, Digital Input (Active Low). Bringing this pin low enables the AD9957 to detect
serial clock rising/falling edges. Bringing this pin high causes the AD9957 to ignore input
on the serial data pins.
71
I/O_RESET
I
Input/Output Reset, Digital Input (Active High). Rather than resetting the entire device
during a failed communication cycle, when brought high, this pin resets the state machine
of the serial port controller and clears any I/O buffers that have been written since the last
I/O update. When unused, tie this pin to ground to avoid accidental resets.
80
IOUT
O
Open-Source DAC Complementary Output Source. Analog output, current mode. Connect
through 50 to AGND.
81
IOUT
O
Open-Source DAC Output Source. Analog output, current mode. Connect through 50 to
AGND.
84
DAC_RSET
O
Analog Reference Pin. This pin programs the DAC output full-scale reference current.
Attach a 10 k resistor to AGND.
90
REF_CLK
I
Reference Clock Input. Analog input. See the REFCLK Overview section for more details.
91
REF_CLK
I
Complementary Reference Clock Input. Analog input. See the REFCLK Overview section
for more details.
94
REFCLK_OUT
O
Reference Clock Output. Analog output. See the REFCLK Overview section for more
details.
95
XTAL_SEL
I
Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high enables
the internal oscillator to be used with a crystal resonator. If unused, connect it to AGND.
(EPAD)
Exposed Pad
(EPAD)
The EPAD should be soldered to ground.
1
I = input, O = output.
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