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參數(shù)資料
| 型號： | AD9957BSVZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT IQ 100TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1,000 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD |
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AD9957
Data Sheet
Rev. C | Page 34 of 64
CLOCK INPUT (REF_CLK)
REFCLK OVERVIEW
The AD9957 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK/REF_CLK input pins. The REF_CLK input can be
driven directly from a differential or single-ended source, or it
can accept a crystal connected across the two input pins. There
is also an internal phase-locked loop (PLL) multiplier that can
be independently enabled. A block diagram of the REF_CLK
functionality is shown in Figure 47. The various input configu-
rations are controlled by means of the XTAL_SEL pin and
control bits in the CFR3 register. Figure 47 also shows how the
CFR3 control bits are associated with specific functional blocks.
REF_CLK
PLL
VCO
SELECT
DIVIDE
CHARGE
PUMP
OUT
IN
PLL_LOOP_FILTER
ENABLE
PLL_LOOP_FILTER
DRV0
CFR3
<29:28>
REFCLK_OUT
XTAL_SEL
REFCLK
INPUT
SELECT
LOGIC
SYSCLK
ICP
CFR3
<21:19>
N
CFR3
<7:1>
VCO SEL
CFR3
<26:24>
÷2
REFCLK INPUT
DIVIDER BYPASS
CFR3<15>
PLL ENABLE
CFR3
<8>
REFCLK INPUT
DIVIDER RESETB
CFR3<14>
94
95
2
90
91
0
1
0
1
2
7
3
0
1
06384-
028
Figure 47. REF_CLK Block Diagram
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected, the
REF_CLK/REF_CLK pins must be driven by an external signal
source. Input frequencies up to 2 GHz are supported. For input
frequencies greater than 1 GHz, the input divider must be
enabled for proper operation of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected, because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT
buffer is controlled by two bits as listed in Table 6.
Table 6. REFCLK_OUT Buffer Control
CFR3<29:28>
REFCLK_OUT Buffer
00
Disabled
01
Low output current
10
Medium output current
11
High output current
CRYSTAL DRIVEN REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 48 shows
the recommended circuit configuration.
06384-
027
REF_CLK
39pF
XTAL
90
91
Figure 48. Crystal Connection Diagram
DIRECT DRIVEN REF_CLK
When driving the REF_CLK/REF_CLK inputs directly from a
signal source, either single-ended or differential signals can be
used. With a differential signal source, the REF_CLK/REF_CLK
pins are driven with complementary signals and ac-coupled
with 0.1 F capacitors. With a single-ended signal source, either a
single-ended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either case,
0.1 F capacitors are used to ac couple both REF_CLK/REF_CLK
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 49 for more details.
The REF_CLK/REF_CLK input resistance is ~2.5 k differential
(~1.2 k single-ended). Most signal sources have relatively low
output impedances. The REF_CLK/REF_CLK input resistance is
relatively high; therefore, its effect on the termination impedance
is negligible and can usually be chosen to be the same as the output
impedance of the signal source. The bottom two examples in
Figure 49 assume a signal source with a 50 output impedance.
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