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參數(shù)資料
| 型號： | AD9954YSVZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48TQFP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 500 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9954/PCBZ-ND - BOARD EVAL FOR 9954 |
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AD9954
Rev. B | Page 9 of 40
Pin No.
Mnemonic
I/O
Description
31
COMP_IN
I
Comparator Complementary Input.
35
PWRDWNCTL
I
Input Pin Used as an External Power-Down Control (see Table 9 for details).
36
RESET
I
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the default
state, as described in the right-hand column of Table 12, which is the I/O port register map.
37
IOSYNC
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once
IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.
38
SDO
O
See Serial Interface Port Pin Description section for details.
39
CS
I
See Serial Interface Port Pin Description section for details.
40
SCLK
I
See Serial Interface Port Pin Description section for details.
41
SDIO
I/O
See Serial Interface Port Pin Description section for details.
43
DVDD_I/O
I
Digital Power Supply. This pin is for I/O cells only, 3.3 V.
44
SYNC_IN
I
Input Signal Used to Synchronize Multiple AD9954s. This input is connected to the SYNC_CLK
output of a master AD9954.
45
SYNC_CLK
O
Clock Output Pin that Serves as a Synchronizer for External Hardware.
46
OSK
I
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function When Programmed
for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is disabled, this pin should
be tied to DGND.
47, 48
PS0, PS1
I
Input Pins Used to Select One of the Internal Phase/Frequency Profiles. PS1 and PS0 are
synchronous to the SYNC_CLK pin. Change on these pins triggers a transfer of the contents of
the chosen internal buffer memory to the I/O registers (sends an internal I/O UPDATE).
<49>
AGND
I
The Exposed Paddle on the Bottom of the Package. It is a ground connection for the DAC and
must be attached to AGND in any board layout.
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| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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