- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9954YSVZ-REEL7 (Analog Devices Inc)IC DDS DAC 14BIT 1.8V 48TQFP PDF資料下載
參數(shù)資料
| 型號： | AD9954YSVZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9954/PCBZ-ND - BOARD EVAL FOR 9954 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
AD9954
Rev. B | Page 19 of 40
03
37
4-
00
3
FTW0
SINGLE-TONE
MODE
LINEAR SWEEP MODE
AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW.
AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW.
PS<0> = 1
PS<0>= 0
PS<0> =0
TIME
FTW1
A
B
fOUT
Figure 21. Linear Sweep Frequency Plan
03
37
4-
00
4
FTW0
SINGLE-TONE
MODE
LINEAR SWEEP MODE ENABLE–NO DWELL BIT SET
FTW1
AA
A
B
BB
fOUT
TIME
PS<0> = 1 PS<0> = 0
PS<0> = 0
PS<0> = 1
PS<0> = 0
Figure 22. Linear Sweep Using No-Dwell Frequency Plan
Linear Sweep No-Dwell Feature
See CFR1<2> in the register maps (see Table 12 and Table 13)
for general details of the no-dwell mode. Figure 22 depicts the
linear sweep mode operation when the linear sweep no-dwell
bit is set. The Label A points indicate where a rising edge on
PS0 is detected; the Label B points indicate where the AD9954
has determined fOUT has reached the terminal frequency and
automatically returns to the starting frequency. Note that in this
mode, only sweeps from FTW0 to FTW1 using the positive
linear sweep control word are supported. Toggling PS0 from 1
to 0 neither initiates a falling sweep when the no-dwell bit is set,
nor interrupts a positive sweep already underway.
Resetting the Ramp Rate Timer
The ramp timer can be reset before reaching a count of 1 by
three methods.
Method one is by changing the PS0 input pin. When the PS0
input pin toggles from 0 to 1, the RSRRW value is loaded into
the ramp rate timer, which then proceeds to countdown as
normal. When the PS0 input pin toggles from 0 to 1, the falling
sweep ramp rate word (FSRRW) value is loaded into the ramp
rate timer, which then proceeds to countdown as normal.
The second method uses the LOAD SRR @ I/O UD bit
(CFR1<15>), see Table 12 for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9956YCPZ-REEL7 | IC SYNTHESIZER 1.8V 48LFCSP |
| AD9957BSVZ-REEL | IC DDS 1GSPS 14BIT IQ 100TQFP |
| AD9958BCPZ-REEL7 | IC DDS DUAL 10BIT DAC 56LFCSP |
| AD9959BCPZ-REEL7 | IC DDS QUAD 10BIT DAC 56LFCSP |
| AD9970BCPZRL7 | IC PROCESSOR CCD SIGNAL 32-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9955KS6 | 制造商:AD 功能描述:* |
| AD9955KS-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9955KS-66 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| AD9956 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。