參數(shù)資料
型號: AD9951YSVZ
廠商: Analog Devices Inc
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC DDS DAC 14BIT 1.8V 48-TQFP
產(chǎn)品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝: 1
分辨率(位): 14 b
主 fclk: 400MHz
調節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
AD9951
Rev. A | Page 13 of 28
DAC Output
The AD9951 incorporates an integrated 14-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND.
Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
full-scale current is controlled by an external resistor (RSET)
connected between the DAC_RSET pin and the DAC ground
(AGND_DAC). The full-scale current is proportional to the
resistor value as follows:
OUT
SET
I
R
/
19
.
39
=
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.
Voltages developed beyond this range will cause excessive DAC
distortion and could potentially damage the DAC output circuitry.
Proper attention should be paid to the load termination to keep the
output voltage within this compliance range.
Serial IO Port
The AD9951 serial port is a flexible, synchronous serial
communications port that allows easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O port
is compatible with most synchronous transfer formats, including
both the Motorola 6905/11 SPI and Intel 8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9951. MSB first or LSB first transfer formats are supported.
The AD9951’s serial interface port can be configured as a single pin
I/O (SDIO), which allows a 2-wire interface or two unidirectional
pins for in/out (SDIO/SDO), which in turn enables a 3-wire
interface. Two optional pins, IOSYNC and CS
Register Map and Descriptions
, enable greater
flexibility for system design in the AD9951.
The register map is listed in Table 5.
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