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參數(shù)資料
| 型號： | AD9951YSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9951
Rev. A | Page 21 of 28
There are two phases to a communication cycle with the
AD9951. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9951, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9951 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9951. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9951
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register No. 2, which is three bytes wide, Phase 2 requires
that three bytes be transferred. If accessing the frequency tuning
word, which is four bytes wide, Phase 2 requires that four bytes
be transferred. After transferring all data bytes per the instruc-
tion, the communication cycle is completed.
At the completion of any communication cycle, the AD9951
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9951 is registered on the rising edge of
SCLK. All data is driven out of the AD9951 on the falling edge
of SCLK. Figure 21 through Figure 24 are useful in understand-
ing the general operation of the AD9951 serial port.
0
33
59
-00
8
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 21. Serial Port Write Timing–Clock Stall Low
03
35
9-
00
9
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
DO 5 DO 4 DO 3 DO 2 DO 1
DO 0
DO 7 DO 6
SDO
CS
Figure 22. 3-Wire Serial Port Read Timing–Clock Stall Low
03
35
9-
01
0
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 23. Serial Port Write Timing–Clock Stall High
0
33
59-
01
1
I6
I5
I4
I3
I2
I1
DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
I0
DO 7 DO 6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High
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