參數(shù)資料
型號(hào)： AD9951YSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： IC DDS DAC 14BIT 1.8V 48-TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 400MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-TQFP 裸露焊盤(pán)（7x7）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
AD9951
Rev. A | Page 8 of 28
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions—48-Lead TQFP/EP
Pin No.
Mnemonic
I/O
Description
1
I/O UPDATE
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin
must be set up and held around the SYNC_CLK output signal.
2, 34
DVDD
I
Digital Power Supply Pins (1.8 V).
3, 33, 42, 47,
48
DGND
I
Digital Power Ground Pins.
4, 6, 13, 16,
18, 19, 25,
27, 29
AVDD
I
Analog Power Supply Pins (1.8 V).
5, 7, 14, 15,
17, 22, 26,
28, 30, 31,
32
AGND
I
Analog Power Ground Pins.
8
OSC/
I
REFCLK
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-
ended mode, REFCLKB should be decoupled to AVDD with a 0.1 F capacitor.
9
OSC/REFCLK
I
Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK
operation.
10
CRYSTAL OUT
O
Output of the Oscillator Section.
11
CLKMODESELECT
I
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the
oscillator section is bypassed.
12
LOOP_FILTER
I
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 k resistor in series with a 0.1 F capacitor
tied to AVDD.
20
IOUT
O
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
21
IOUT
O
DAC Output. Should be biased through a resistor to AVDD, not AGND.
23
DACBP
I
DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
24
DAC_R
SET
I
A resistor (3.92 k nominal) connected from AGND to DAC_R
SET establishes the reference current
for the DAC.
35
PWRDWNCTL
I
Input Pin Used as an External Power-Down Control (see Table 8 for details).
36
RESET
I
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9951 to the initial state,
as described in the I/O port register map.
37
IOSYNC
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is
returned low. If unused, ground this pin; do not allow this pin to float.
38
SDO
O
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When
operated as a 2-wire serial port, this pin is unused and can be left unconnected.
39
CS
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
40
SCLK
I
This pin functions as the serial data clock for I/O operations.
41
SDIO
I/O
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input, only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
43
DVDD_I/O
I
Digital Power Supply (for I/O Cells Only, 3.3 V).
44
SYNC_IN
I
Input Signal Used to Synchronize Multiple AD9951s. This input is connected to the SYNC_CLK
output of a master AD9951.
45
SYNC_CLK
O
Clock Output Pin that Serves as a Synchronizer for External Hardware.
46
OSK
I
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when Programmed
for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin
should be tied to DGND.
<49>
AGND
I
The exposed paddle on the bottom of the package is a ground connection for the DAC and must
be attached to AGND in any board layout.
相關(guān)PDF資料
PDF描述
AD9952YSVZ-REEL7 IC DDS DAC 14BIT 1.8V 48TQFP
AD9953YSVZ-REEL7 IC DDS DAC 14BIT 1.8V 48TQFP
AD9954YSVZ-REEL7 IC DDS DAC 14BIT 1.8V 48TQFP
AD9956YCPZ-REEL7 IC SYNTHESIZER 1.8V 48LFCSP
AD9957BSVZ-REEL IC DDS 1GSPS 14BIT IQ 100TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9951YSVZ-REEL7 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48TQFP EP TAPE AND REEL - Tape and Reel
AD9952 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
AD9952/PCB 制造商:Analog Devices 功能描述:Evaluation Board For Digital Synthesizer 制造商:Analog Devices 功能描述:400 MSPS 14BIT CMOS DIRECT DGTL SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9952YSV 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48
AD9952YSV-REEL7 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*