- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373970 > AD9923ABBCZRL (ANALOG DEVICES INC) CCD Signal Processor with V-Driver and Precision Timing⑩ Generator PDF資料下載
參數(shù)資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 72/88頁 |
| 文件大?。?/td> | 852K |
| 代理商： | AD9923ABBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當(dāng)前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
AD9923A
Table 48. Timing Core Registers
Address
(Hex)
Bits
30
[0]
31
[5:0]
[13:8]
[16]
32
[5:0]
[13:8]
[16]
33
[5:0]
[13:8]
[16]
34
[5:0]
[13:8]
[16]
35
[0]
Rev. 0 | Page 72 of 88
Data
Default
Value
0
0
20
1
0
20
1
0
20
1
0
10
1
0
Update
Type
SCK
SCK
SCK
SCK
SCK
VD
Name
CLIDIVIDE
H1POSLOC
H1NEGLOC
H1H2POL
H3POSLOC
H3NEGLOC
H3H4POL
HLPOSLOC
HLNEGLOC
HLPOL
RGPOSLOC
RGNEGLOC
RGPOL
H1H2RETIME
Description
Divide CLI input frequency by 2.
0: no divide.
1: divide by 2.
H1 rising edge location.
H1 falling edge location.
H1/H2 polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
H3 rising edge location.
H3 falling edge location.
H3/H4 polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
HL rising edge location.
HL falling edge location.
HL polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
RG rising edge location.
RG falling edge location.
RG polarity control.
0: inverse of convention in Figure 18.
1: no inversion.
Retime HBLK for H1/H2 to the internal H1 clock. The preferred setting is 1,
which adds one cycle of delay to the HBLK toggle positions.
0: no retime.
1: retime.
Retime HBLK for H3/H4 to the internal H3 clock.
Retime HBLK for HL to the internal HL clock.
Enable HBLK for HL output.
0: disable.
1: enable.
Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0: same frequency as pixel rate.
1: 1/2 pixel frequency, that is, it doubles the H1 to H4 pulse width.
2: 1/4 pixel frequency.
3: 1/6 pixel frequency.
4: 1/8 pixel frequency.
5: 1/10 pixel frequency.
6: 1/12 pixel frequency.
7: 1/14 pixel frequency.
H1 drive strength.
0: off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 17.2 mA.
5: 21.5 mA.
6: 25.8 mA.
7: 30.1 mA.
36
[1]
[2]
[3]
[6:4]
[3:0]
0
0
0
0
1
SCK
H3H4RETIME
HLRETIME
HLHBLKEN
HBLKWIDTH
H1DRV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9925BBCZRL | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。