參數(shù)資料
型號(hào)： AD9923ABBCZRL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁(yè)數(shù)： 27/88頁(yè)
文件大?。?/td> 852K
代理商： AD9923ABBCZRL
AD9923A
Vertical Sequences (VSEQ)
A vertical sequence (VSEQ) is created by selecting one of the
V-pattern groups and adding repeats, a start position, and
horizontal clamping and blanking information. Each VSEQ is
programmed using the registers shown in Table 15. Figure 37
shows how each register is used to generate a V-sequence.
Rev. 0 | Page 27 of 88
The VPATSELA and VPATSELB registers select the V-pattern
group that is used in a given V-sequence. Having two groups
available allows each vertical output to be mapped to a different
V-pattern group. The selected V-pattern group can have
repetitions added for high speed line shifts or line binning by
using the VREP registers for odd and even lines. Generally, the
same number of repetitions is programmed into both registers.
If a different number of repetitions is required on odd and even
lines, separate values can be used for each register (see the
Generating Line Alternation for V-Sequences and HBLK
section). The VSTARTA and VSTARTB registers specify the pixel
location where the V-pattern group starts. The VMASK register is
used in conjunction with the FREEZE/RESUME registers to enable
optional masking of the XV outputs. Either or both of the
FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be
enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. Note that the last line of the
field can be programmed separately using the HDLAST register,
located in the field register (see Table 16).
VREP 3
HD
XV1 TO XV13
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1
START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP.
2
HD LINE LENGTH.
3
V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
4
NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
5
START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
6
MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
V-PATTERN GROUP
1
3
CLPOB
PBLK
HBLK
2
4
4
VREP 2
5
6
0
Figure 37. V-Sequence Programmability
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參數(shù)描述
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