參數(shù)資料
型號(hào)： AD9923ABBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁數(shù)： 60/88頁
文件大?。?/td> 852K
代理商： AD9923ABBCZ
AD9923A
Rev. 0 | Page 60 of 88
H-COUNTER
RESET
VD
NOTES
1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 33 OR 34 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 34 CLI RISING EDGES AFTER HD FALLING EDGE.
Figure 77. External VD/HD and Internal H-Counter Synchronization, Slave Mode
HD
CLI
X
X
X
X
X
X
X
X
H-COUNTER
(PIXEL COUNTER)
3ns MIN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3ns MIN
SHD
INTERNAL
HD
INTERNAL
t
CLIDLY
X
32.5 CYCLES
0
1
2
X
X
X
X
X
X
X
X
X
0
0
0
1
2
3
4
H-COUNTER
RESET
VD
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.
Figure 78. Toggle Position Inhibited Area—Master Mode
HD
H-COUNTER
(PIXEL COUNTER)
N
N-1
N-2
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-13
N-14
N-15
N-16
N-17
N-18
N-19
N-20
N-21
N-22
N-23
N-24
N-25
N-26
N-27
N-28
0
H-RESET
VD
NOTES
HD
(PIXEH-COUNTER
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
0
1
2
N-1
N
N-2
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-13
N-14
N-15
N-16
N-17
N-18
N-19
N-20
N-21
N-22
N-23
N-24
N-25
N-26
N-27
N-28
N-29
N-30
N-31
N-32
N-33
Figure 79. Toggle Position Inhibited Area—Slave Mode
Vertical Toggle Position Placement Near Counter Reset
One additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 28 pixels
during which no toggle positions can be programmed.
As shown in Figure 78, in master mode, the last 28 pixels before
the HD falling edge should not be used for toggle position place-
ment of the XV, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
Figure 79 shows the same example for slave mode. The same
restriction applies—the last 28 pixels before the counters are
reset cannot be used. However, the counter reset is delayed with
respect to VD/HD placement; therefore, the inhibited area is
different than it is in master mode.
It is also recommended that Pixel Location 0 is not used for
toggle positions for the VSG and SUBCK pulses.
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