參數(shù)資料
型號(hào): AD9913BCPZ-REEL71
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
中文描述: 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器
文件頁(yè)數(shù): 4/32頁(yè)
文件大?。?/td> 473K
代理商: AD9913BCPZ-REEL71
AD9913
Parameter
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time
1
Fast Recovery Mode
Full Sleep Mode
Reset Pulse Width High
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Frequency-to-DAC Output
Phase-to-DAC Output
Delta Tuning Word-to-DAC Output (Linear Sweep)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
DAC_CLK_AVDD (1.8 V)
DAC_AVDD (1.8 V) Pin Current Consumption
PLL_AVDD (1.8 V)
CLK_AVDD (1.8 V) Pin Current Consumption
POWER CONSUMPTION
Single Tone Mode
Modulus Mode
Linear Sweep Mode
Power-Down
Full
Safe
PLL Modes
VCO 1
Differential Input Mode
CMOS Input Mode
Crystal Mode
VCO 2
Differential Input Mode
CMOS Input Mode
Crystal Mode
1
Refer to the Power-Down Features section.
2
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
Rev. 0 | Page 4 of 32
Conditions/Comments
Matched latency enabled
Matched latency disabled
Matched latency disabled
1 mA load
PLL enabled, CMOS input
PLL disabled, differential input
PLL enabled, XTAL input
PLL disabled
PLL disabled
PLL enabled
Min
5
1.2
700
700
1.5
Typ
11
11
10
14
3
50
57
52
Max
1
60
0.4
+700
+700
0.125
46.5
4.7
6.2
1.8
4.3
66.5
70.5
68.5
94.6
98.4
15
44.8
11
7.5
5.4
15
11.5
9.4
Unit
SYSCLK cycles
2
μs
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
V
nA
nA
pF
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
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