參數(shù)資料
型號(hào)： AD9913BCPZ-REEL71
廠商： Analog Devices, Inc.
元件分類(lèi)： XO, clock
英文描述： Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
中文描述： 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 473K
代理商： AD9913BCPZ-REEL71
AD9913
Control Function Register 2 (CFR2)
Address 0x01; 2 bytes are assigned to this register.
Table 11. Bit Descriptions for CFR2
Bit(s)
Bit Name
15
PLL Output Div by 2
14:9
PLL Multiplication Factor
8
Open
7
CMOS Clock Mode
6
Crystal Clock Mode
5
PLL Power-Down
Rev. 0 | Page 29 of 32
Description
See
Table 7
for details on multiplication factor configuration.
Leave this bit at the default state.
See Table 6 for directions on programming this bit.
See Table 6 for directions on programming this bit.
0 = PLL is active
1 = PLL is inactive and in its lowest power state
0 = use this setting for PLL if the PLL reference frequency is >5 MHz.
1 = use this setting for PLL if the PLL reference frequency is <5 MHz.
0 = the PLL reference frequency = the REF_CLK input frequency.
1 = the PLL reference frequency = the REF_CLK input frequency.
0 = use this setting for VCO frequencies below 100 MHz and/or to optimize for power rather
than performance.
1 = use this setting to optimize for performance; this setting results in slightly higher power
consumption. Note: When setting this bit, an IO_UPDATE must occur within 40
μ
s of the PLL
power-down bit (CFR2 [5]) going low.
0 = the PLL logic is reset and non-operational until this bit is set.
1 = the PLL logic operates normally.
This read-only bit is set when the REF_CLK PLL is locked.
4
3
2
PLL LO Range
PLL Input Div by 2
VCO2 Sel
1
0
PLL Reset
PLL Lock
DAC Control Register
Address 0x02; 4 bytes are assigned to this register.
Table 12. Bit Descriptions for DAC Control Register
Bit(s)
Bit Name
15:14, 10
Open
9:0
FSC
31:16,13:11
Reserved
Frequency Tuning Word Register (FTW)
Address 0x03, 4 bytes are assigned to this register.
Table 13. Bit Descriptions for FTW Register
Bit(s)
Bit Name
31:0
Frequency Tuning Word
Phase Offset Word Register (POW)
Address 0x04, 2 bytes are assigned to this register.
Table 14. Bit Descriptions for POW Register
Bit(s)
Bit Name
15:14
Open
13:0
Phase Offset Word
Description
Leave these bits at their default state.
This 10-bit number controls the full-scale output current of the DAC.
Leave these bits at their default state.
Description
32-bit frequency tuning word.
Description
Leave these bits at their default state.
14-bit phase offset word.
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