參數(shù)資料
型號(hào)： AD9912ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/40頁(yè)
文件大小： 0K
描述： IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
AD9912
Rev. F | Page 12 of 40
06
76
3-
0
09
19.85
19.95
20.05
20.15
20.25
20.35
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
S
IG
NAL
P
O
W
E
R
(d
Bm)
20.1MHz
–95dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 9. Narrow-Band SFDR at 20.1 MHz,
SYSCLK = 1 GHz (SYSCLK PLL Bypassed)
06
76
3-
0
10
200.85
200.95
201.05
201.15
201.25
201.35
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
S
IG
NAL
P
O
W
E
R
(d
Bm)
201.1MHz
–91dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 10. Narrow-Band SFDR at 201.1 MHz,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06
76
3-
0
11
398.45
398.55
398.65
398.75
398.85
398.95
FREQUENCY (MHz)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
S
IG
NAL
P
O
W
E
R
(d
Bm)
398.7MHz
–86dBc
500kHz
300Hz
1kHz
CARRIER:
SFDR:
FREQ. SPAN:
RESOLUTION BW:
VIDEO BW:
Figure 11. Narrow-Band SFDR at 398.7 MHz,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06
76
3-
0
12
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
P
HAS
E
NO
IS
E
(
d
Bc/
H
z
)
399MHz
99MHz
RMS JITTER (100Hz TO 40MHz):
99MHz:
399MHz:
413fs
222fs
Figure 12. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06
76
3-
0
13
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
P
HAS
E
NO
IS
E
(
d
Bc/
H
z
)
399MHz
99MHz
RMS JITTER (12kHz TO 20MHz):
99MHz:
399MHz:
0.98ps
0.99ps
Figure 13. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 83.33 MHz )
06
76
3-
0
14
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–80
–90
–100
–110
–120
–130
–140
–150
–160
P
HAS
E
NO
IS
E
(
d
Bc/
H
z
)
399MHz
99MHz
RMS JITTER (12kHz TO 20MHz):
99MHz:
399MHz:
1.41ps
1.46ps
Figure 14. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal
Generator at 25 MHz )
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