參數(shù)資料
型號(hào)： AD9912ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/40頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9912
Rev. F | Page 34 of 40
Register 0x0011—Reserved
Register 0x0012—Reset (Autoclearing)
To reset the entire chip, the user can use the (non-autoclearing) soft reset bit in Register 0x0000.
Table 17.
Bits
Bit Name
Description
0
DDS reset
Reset of the direct digital synthesis block. Reset of this block is very seldom needed.
Register 0x0013—Reset (Continued) (Not Autoclearing)
Table 18.
Bits
Bit Name
Description
7
PD fund DDS
Setting this bit powers down the DDS fundamental output but not the spurs. It is used during tuning
of the SpurKiller circuit.
3
S-div/2 reset
Asynchronous reset for S prescaler.
1
S-divider reset
Synchronous (to S-divider prescaler output) reset for integer divider.
SYSTEM CLOCK (REGISTER 0x0020 TO REGISTER 0x0022)
Register 0x0020—N-Divider
Table 19.
Bits
Bit Name
Description
[4:0]
N-divider
These bits set the feedback divider for system clock PLL. There is a fixed divide-by-2 preceding this
block, as well as an offset of 2 added to this value. Therefore, setting this register to 00000 translates to
an overall feedback divider ratio of 4. See Figure 45.
Register 0x0021—Reserved
Register 0x0022—PLL Parameters
Table 20.
Bits
Bit Name
Description
7
VCO auto range
Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
[6:4]
Reserved
Reserved.
3
2× reference
Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by
the SYSCLK PLL. See Figure 44.
2
VCO range
Selects low range or high range VCO.
0 = low range (700 MHz to 810 MHz).
1 = high range (900 MHz to 1000 MHz). For system clock settings between 810 MHz and 900 MHz, use
the VCO auto range (Bit 7) to set the correct VCO range automatically.
[1:0]
Charge pump current
Charge pump current.
00 = 250 μA.
01 = 375 μA.
10 = off.
11= 125 μA.
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