Changed Default Value of Register 0x003 to 0x19 (
參數(shù)資料
型號(hào): AD9912ABCPZ
廠商: Analog Devices Inc
文件頁數(shù): 23/40頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 48 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9912
Rev. F | Page 3 of 40
REVISION HISTORY
6/10—Rev. E to Rev. F
Changed Default Value of Register 0x003 to 0x19 (Table 12).....31
5/10—Rev. D to Rev. E
Deleted 64-Lead LFCSP (CP-64-1).................................. Universal
Changes to SYSCLK PLL Enabled/ Maximum Input Rate of System
Clock PFD, Table 2
...............................................................................6
Updated Outline Dimensions........................................................39
Changes to Ordering Guide...........................................................39
11/09—Rev. C to Rev. D
Added 64-Lead LFCSP (CP-64-7).................................... Universal
Changes to Serial Port Timing Specifications and
Propagation Delay Parameters ........................................................6
Added Exposed Paddle Notation to Figure 2 ................................8
Changes to Power Supply Partitioning Section...........................25
Change to Serial Control Port Section .........................................26
Changes to Figure 52 ......................................................................28
Added Exposed Paddle Notation to Outline Dimensions.........38
Changes to Ordering Guide...........................................................39
7/09—Rev. B to Rev. C
Changes to Logic Outputs Parameter, Table 1 ..............................3
Changes to AVDD (Pin 25, Pin 26, Pin 29, and Pin 30) ............25
6/09—Rev. A to Rev. B
Changes to Figure 40 and Direct Digital Synthesizer Section ..17
Changes to Figure 48 ......................................................................22
Changes to Table 11 ........................................................................30
Changes to Table 22 and Table 23.................................................34
1/08—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................3
Changes to Table 2 ............................................................................5
Changes to Table 4 ............................................................................8
Changes to Typical Performance Characteristics .......................10
Changes to Functional Description Section................................19
Changes to Single-Ended CMOS Output Section ......................21
Changes to Harmonic Spur Reduction Section ..........................21
Changes to Power Supply Partitioning Section...........................25
10/07—Revision 0: Initial Version
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