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| 型號(hào)： | AD9882KSTZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 39/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/DVI 100MHZ 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬，DVI |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9882A
Rev. 0 | Page 8 of 40
Pin Type
Mnemonic
Function
Value
Pin
Number
Interface
Data Outputs
RED [7:0]
Outputs of Converter Red, Bit 7 is the MSB
3.3 V CMOS
92–99
Both
GREEN [7:0]
Outputs of Converter Green, Bit 7 is the MSB
3.3 V CMOS
2–9
Both
BLUE [7:0]
Outputs of Converter Bue, Bit 7 is the MSB
3.3 V CMOS
12–19
Both
Data Clock Output
DATACK
Data Output Clock for the Analog and Digital
Interface
3.3 V CMOS
85
Both
RX0+
Digital Input Channel 0 True
33
Digital
Digital Video Data
Inputs
RX0–
Digital Input Channel 0 Complement
32
Digital
RX1+
Digital Input Channel 1 True
36
Digital
RX1–
Digital Input Channel 1 Complement
35
Digital
RX2+
Digital Input Channel 2 True
39
Digital
RX2–
Digital Input Channel 2 Complement
38
Digital
RXC+
Digital Data Clock True
41
Digital
Digital Video Clock
Inputs
RXC–
Digital Data Clock Complement
42
Digital
Data Enable
DE
Data Enable
3.3 V CMOS
86
Digital
Control Bits
CTL [0:3]
Decoded Control Bits
3.3 V CMOS
22–25
Digital
RTERM
RTERM
Sets Internal Termination Resistance
28
Digital
HDCP
DDCSCL
HDCP Slave Serial Port Data Clock
3.3 V CMOS
53
Digital
DDCSDA
HDCP Slave Serial Port Data I/O
3.3 V CMOS
54
Digital
MCL
HDCP Master Serial Port Data Clock
3.3 V CMOS
81
Digital
MDA
HDCP Master Serial Port Data I/O
3.3 V CMOS
82
Digital
PIN DESCRIPTIONS OF SHARED PINS BETWEEN
ANALOG AND DIGITAL INTERFACES
HSOUT—Horizontal Sync Output
A reconstructed and phase-aligned version of the video Hsync.
The polarity of this output can be controlled via a serial bus bit.
In analog interface mode, the placement and duration are
variable. In digital interface mode, the placement and duration
are set by the graphics transmitter.
VSOUT—Vertical Sync Output
The separated Vsync from a composite signal or a direct pass-
through of the Vsync input. The polarity of this output can be
controlled via a serial bus bit. The placement and duration in all
modes is set by the graphics transmitter.
SERIAL PORT (2-WIRE)
SDA—Serial Port Data I/O
SCL—Serial Port Data Clock
A0—Serial Port Address Input
For a full description of the 2-wire serial register, refer to the
DATA OUTPUTS
RED—Data Output, Red Channel
GREEN—Data Output, Green Channel
BLUE—Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. These outputs are
shared between the two interfaces and behave in accordance
with the active interface. Refer to the Analog Interface and
Digital Interface sections.
DATACK—Data Output Clock
Just like the data outputs, the data clock output is shared
between the two interfaces. It behaves differently depending on
which interface is active. Refer to the DATACK—Data Output
section to determine how this pin behaves. .
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| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
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