參數(shù)資料
型號(hào)： AD9882KSTZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE/DVI 100MHZ 100LQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9882A
Rev. 0 | Page 26 of 40
2-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
0x00 7–0
Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01 7–0
PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a pixel clock from the incoming Hsync signal.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV
value determines the number of pixel times (pixels plus hori-
zontal blanking overhead) per line. This is typically 20% to 30%
more than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
221 to 4095. The higher the value loaded in this register, the
higher the resulting clock frequency with respect to a fixed
Hsync frequency.
VESA has established some standard timing specifications that
can assist in determining the value for PLLDIV as a function of
the horizontal and vertical display resolution and frame rate
(see Table 10). However, many computer systems do not con-
form precisely to the recommendations, and these numbers
should be used only as a guide. The display system manu-
facturer should provide automatic or manual means for
optimizing PLLDIV. An incorrectly set PLLDIV usually
produces one or more vertical noise bars on the display. The
greater the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9882A updates the full divide ratio only when the LSBs
are changed. Writing to this register by itself does not trigger an
update.
0x02 7–4
PLL Divide Ratio LSBs
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9882A updates the full divide ratio only when this
register is written.
0x03 7–6
VCO Range Select
Two bits that establish the operating range of the clock
generator. VCORNGE must be set to correspond with the
desired operating frequency (incoming pixel rate).
The PLL VCO gives the best jitter performance while operating
at high frequencies. For this reason, to output low pixel rates
and still get good jitter performance, the PLL VCO actually
operates at a higher frequency but then divides down the clock
rate afterward. Table 13 shows the pixel rates for each VCO
range setting. The PLL output divisor is automatically selected
with the VCO range setting.
Table 13. VCO Ranges
VCORNGE
Pixel Rate Range
00
12–41
01
41–82
10
82–140
The power-up default value is VCORNGE = 01.
0x03 5–3
CURRENT Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator.
Table 14. Charge Pump Currents
Charge Pump
Current (A)
000
50
001
100
010
150
011
250
100
350
101
500
110
750
111
1500
Charge pump must be set to correspond with the desired
operating frequency (incoming pixel rate). See Table 10 for
the charge pump current for each register setting.
The power-up default value for current is 001.
0x04 7–3
Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps across
one pixel time. Each step represents an 11.25° shift in sampling
phase.
The power-up default phase adjust value is 0x10.
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