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參數(shù)資料
| 型號： | AD9882KSTZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/DVI 100MHZ 100LQFP |
| 標準包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬，DVI |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9882A
Rev. 0 | Page 30 of 40
0x11 1 Coast Input Polarity
This bit indicates the polarity of the coast signal that is applied
to the PLL coast input.
This register can be used only when coast is disabled and
Register 0x11, Bit 2 is set to 1.
Table 31. Coast Input Polarity Settings
CSTPOL
Function
0
Active low
1
Active high
The power-up default value is CSTPOL = 1.
0x12 7–0
Precoast
This register allows the coast signal to be applied prior to the
Vsync signal. This is necessary in cases where pre-equalization
pulses are present. This register defines the number of edges
that are filtered before Vsync on a composite sync.
The default is 0.
0x13 7–0 Postcoast
This register allows the coast signal to be applied following the
Vsync signal. This is necessary in cases where postequalization
pulses are present. The step size for this control is one Hsync
period. This register defines the number of edges that are
filtered after Vsync on a composite sync.
The default is 0.
0x14 7–6 Output Drive
These two bits select the drive strength for the high speed
digital outputs (all data output and clock output pins). Higher
drive strength results in faster rise/fall times, and in general
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps reduce EMI and digitally
generated power supply noise.
Table 32. Output Drive Strength Settings
Bit 7
Bit 6
Result
1
X
High drive strength
0
1
Medium drive strength
0
Low drive strength
The default for this register is 11, high drive strength. This
option works on both the analog and digital interfaces.
0x14 5
Programmable Analog Bandwidth
These bits select the analog bandwidth.
Table 33. Analog Bandwidth Control
Bit 5
Analog Bandwidth
0
10 MHz
1
300 MHz
0x14 4
Clk Inv Data Output Clock Invert
A control bit for the inversion of the output data clock (Pin 85).
This function works only for the digital interface. When not
inverted, data is output on the falling edge of the data clock. See
how this affects timing.
Table 34. Clock Output Invert Settings
Clk Inv
Function
0
Not inverted
1
Inverted
The default for this register is 0 (not inverted).
0x14 3
PDO Power-Down Outputs
This bit is used to put the outputs in a high impedance mode.
This applies to the 24 data output pins, HSOUT, VSOUT, and
DE pins.
Table 35. Power-Down Output Settings
PDO
Function
0
Normal operation
1
Three-state
The default for this register is 0. (This option works on both the
analog and digital interfaces.)
0x14 2
HDCP Address
This bit is used to set the HDCP slave port address.
Table 36. HDCP Address Settings
Address Bit
Result
0
0 for HDCP Slave Port
1
1 for HDCP Slave Port
The default for this register is 0.
0x14 1
PWRDN
This bit is used to control chip power-down. See the Power
Management section for details about which blocks are actually
powered down.
Table 37. Power-Down Settings
Select
Result
0
Power-down
1
Normal operation
The default for this register is 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883A | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9883A/PCB | 制造商:Analog Devices 功能描述:110MHZ ANALOG INTERFACE FOR SG |
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