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參數(shù)資料
| 型號(hào)： | AD9879BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 5 |
| 功率（瓦特）： | 587mW |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9879
Rev. A | Page 11 of 32
THEORY OF OPERATION
To gain a general understanding of the AD9879, refer to the
block diagram of the device architecture in Figure 3. The
device consists of a transmit path, receive path, and auxiliary
functions, such as a DPLL, a Σ-Δ DAC, a serial control port,
and a cable amplifier interface.
TRANSMIT PATH
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a
12-bit current output DAC. The maximum output current of
the DAC is set by an external resistor. The Tx output PGA
provides additional transmit signal level control.
The transmit path interpolation filter provides an upsampling
factor of 16 with an output signal bandwidth as high as
5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS).
The transmit DAC resolution is 12 bits and can run at sampling
rates as high as 232 MSPS. Analog output scaling from 0.0 dB
to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
DATA ASSEMBLER
The AD9879 data path operates on two 12-bit words, the I and
Q components, which compose a complex symbol. The data
assembler builds the 24-bit complex symbols from four
consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The
nibbles are strobed synchronous to the master clock, MCLK,
into the data assembler. A high level on TxSYNC signals the
start of a transmit symbol. The first two nibbles of the symbol
form the I component, and the second two nibbles form the Q
component. Symbol components are assumed to be in twos
complement format. The timing of the interface is fully
described in the Transmit Timing section of this data sheet.
TXIQ
TXSYNC
MCLK
REFCLK
CA_PORT
PROFILE
SPORT
RXIQ[3:0]
RXSYNC
IF[11:0]
FSADJ
XTAL
OSCIN
Σ-_OUT
FLAG1
I INPUT
Q INPUT
IF10 INPUT
IF12 INPUT
VIDEO INPUT
6
3
12
10
7
12
AD9879
DATA
ASSEMBLER
QUADRATURE
MODULATOR
FIR LPF
CIC LPF
COS
SIN
(fIQCLK)
(fSYSCLK)
(fOSCIN)
(fMCLK)
DAC GAIN CONTROL
PLL
OSCIN
× M
DDS
MUX
CA
INTERFACE
PROFILE
SELECT
SERIAL
INTERFACE
12
4
÷4
SINC–1
MUX
DAC
IQ
IF
CLAMP LEVEL
ADC
MUX
DAC
÷2
÷8
÷4
÷2
12
(fOSCIN)
7
÷R
4
12
I
Q
RXPORT
TX
Σ- INPUT REGISTER
–
+
—
÷2
4
12
—
SINC–1
BYPASS
Σ-
02773-
003
Figure 3. Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9879BSZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9879-EB | 制造商:Analog Devices 功能描述:Evaluation Board For Mixed Signal Front End Set Top Box, Cable Modem 制造商:Analog Devices 功能描述:DEV TOOLS, MIXED SGNL FRONT END SET TOP , CBL MODEM - Bulk |
| AD9880 | 制造商:Analog Devices 功能描述:AUDIO PROCESSOR - Bulk |
| AD9880/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog/HDMI Dual Display Interface |
| AD9880/PCBZ | 功能描述:KIT EVALUATION AD9880 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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