- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9847AKSTZRL (Analog Devices Inc)IC CCD SIGNAL PROC 10BIT 48-LQFP PDF資料下載
參數(shù)資料
| 型號： | AD9847AKSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁
REV. A
AD9847
–9–
SERIAL INTERFACE TIMING
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
XX
SCK
SL
A3
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
VD
HD
SL UPDATED
VD/HD UPDATED
tDS
tDH
tLS
tLH
Figure 3a. Serial Write Operation
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
SCK
SL
A3
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
D0
D1
D2
D3
D4
D5
D0
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
Figure 3b. Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I. SL Updated Registers
Register
Description
Register
Description
oprmode
AFE Operation Modes
ctlmode
AFE Control Modes
preventpdate
Prevents Loading of VD-Updated Registers
readback
Enables Serial Register Readback Mode
vdhdpol
VD/HD Active Polarity
fieldval
Internal Field Pulse Value
hblkretime
Retimes the H1 hblk to Internal Clock
tgcore_rstb
Reset Bar Signal for Internal TG Core
h12pol
H1/H2 Polarity Control
h1posloc
H1 Positive Edge Location
h1negloc
H1 Negative Edge Location
h1drv
H1 Drive Current
h2drv
H2 Drive Current
h3drv
H3 Drive Current
h4drv
H4 Drive Current
rgpol
RG Polarity
rgposloc
RG Positive Edge Location
rgnegloc
RG Negative Edge Location
rgdrv
RG Drive Current
shpposloc
SHP Sample Location
shdposloc
SHD Sample Location
NOTES
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9849AKSTZRL | IC CCD SIGNAL PROC 12BIT 48LQFP |
| AD9850BRS | IC DDS DAC W/COMP 125MHZ 28-SSOP |
| AD9851BRS | IC DDS DAC W/COMP 180MHZ 28-SSOP |
| AD9852ASVZ | IC DDS SYNTHESIZER CMOS 80-TQFP |
| AD9854ASTZ | IC DDS QUADRATURE CMOS 80-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9847KST | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ad9847kstrl | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9848 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processors with Integrated Timing Driver |
| AD9848AKST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Bulk 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS CCD SIGNAL PROCESSOR - Tape and Reel |
| AD9848AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V/3.3V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V 48LQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。