參數資料
型號: AD9847AKSTZRL
廠商: Analog Devices Inc
文件頁數: 19/28頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROC 10BIT 48-LQFP
標準包裝: 2,000
類型: CCD 信號處理器,10 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
REV. A
AD9847
–26–
17
CCD IMAGER
SIGNAL
OUT
18
13
14
20
29
H2
RG
H3
H4
H1
H2
H1
RG
AD9847
CCDIN
Figure 22a. CCD Connections (2 H-Clock)
CCD IMAGER
SIGNAL
OUT
13
14
20
29
RG
H3
H4
H2
H1
RG
AD9847
CCDIN
H2
H1
17
18
H1
H2
Figure 22b. CCD Connections (4 H-Clock)
Driving the CLI Input
The AD9847’s master clock input (CLI) may be used in two
different configurations, depending on the application. Figure 23a
shows a typical dc-coupled input from the master clock source.
When the dc-coupled technique is used, the master clock signal
should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac-coupling capacitor may be used between
the clock source and the CLI input. In this configuration, the CLI
input will self-bias to the proper dc voltage level of approximately
1.4 V. When the ac-coupled technique is used, the master clock
signal can be as low as
±500 mV in amplitude.
CLI
23
MASTER
CLOCK
AD9847
ASIC
Figure 23a. CLI Connection, DC-Coupled
CLI
23
MASTER
CLOCK
AD9847
ASIC
LPF
1nF
Figure 23b. CLI Connection, AC-Coupled
Internal Mode Circuit Configuration
The AD9847 may be used in internal mode using the circuit
configuration of Figure 24. Internal mode uses the same circuit as
Figure 21, except that the horizontal pulses (CLPOB, CLPDM,
PBLK, and HBLK) are internally generated in the AD9847.
These pins may be grounded when internal mode is used. Only
the HD and VD signals are required from the ASIC.
HD/VD
INPUTS
2
44
39
43
42
41
40
HD
VD
PBLK
HBLK
CLPDM
CLPOB
AD9847
Figure 24. Internal Mode Circuit Configuration
TIMING EXAMPLES FOR DIFFERENT SEQUENCES
2
4
48
10
V
H
28
SEQUENCE 3
SEQUENCE 2
Figure 25. Typical CCD
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