參數(shù)資料
型號： AD9847
廠商： Analog Devices, Inc.
英文描述： 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver
中文描述： 10位40 MSPS的CCD信號處理器集成時(shí)序驅(qū)動(dòng)
文件頁數(shù)： 4/28頁
文件大?。?/td> 428K
代理商： AD9847
REV. A
AD9847
TIMING SPECIFICATIONS
–4–
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI to Internal Pixel
Period Position
t
CLI
t
ADC
25
12.5
ns
ns
t
CLIDLY
6
ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
CLPOB Pulsewidth
*
t
CDM
t
COB
4
2
10
20
Pixels
Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge
t
S1
10
ns
DATA OUTPUTS
Output Delay from Programmed Edge
Pipeline Delay
t
OD
6
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
*
Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
(C
L
to 29
pF, f
CLI
= 40 MHz, Serial Timing in Figures 3a and 3b,
unless otherwise noted.)
相關(guān)PDF資料
PDF描述
AD9847AKST 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver
AD9848KST CCD Signal Processors with Integrated Timing Driver
AD9848 CCD Signal Processors with Integrated Timing Driver
AD9849 CCD Signal Processors with Integrated Timing Driver
AD9849KST CCD Signal Processors with Integrated Timing Driver
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