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參數(shù)資料
| 型號(hào)： | AD9847 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| 中文描述： | 10位40 MSPS的CCD信號(hào)處理器集成時(shí)序驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 17/28頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | AD9847 |
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REV. A
AD9847
–17–
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9847
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRV registers. The RG
drive current is adjustable using the RGDRV register. Each 3-bit
DRV register is adjustable in 3.5 mA increments, with the mini-
mum setting of 0 equal to OFF or three-state and the maximum
setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than 1 ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
P[0]
PIXEL
PERIOD
RG
H1/H3
RGf[12]
P[48] = P[0]
Hf[24]
SHP[28]
CCD SIGNAL
P[24]
P[12]
P[36]
Hr[0]
RGr[0]
SHD[48]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
POSITION
t
S1
Figure 6. High Speed Clock Default and Programmable Locations
H2/H4
H1/H3
H1/H3
H2/H4
t
RISE
t
PD
<<
t
RISE
FIXED CROSSOVER VOLTAGE
t
PD
Figure 7. H-Clock Inverse Phase Relationship
Digital Data Outputs
The AD9847 data output phase is programmable using the
DOUTPHASE register. Any edge from 0 to 47 may be programmed,
as shown in Figure 8.
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
P[0]
P[48] = P[0]
CLI
1 PIXEL PERIOD
P[12]
P[24]
P[36]
DOUT
t
OD
Figure 8. Digital Output Phase Adjustment
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9847AKST | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| AD9848KST | CCD Signal Processors with Integrated Timing Driver |
| AD9848 | CCD Signal Processors with Integrated Timing Driver |
| AD9849 | CCD Signal Processors with Integrated Timing Driver |
| AD9849KST | CCD Signal Processors with Integrated Timing Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9847AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9847AKCPZRL | 制造商:Analog Devices 功能描述:DISPLAY DRVR, 10-BIT 40MSPS CCD SGNL PROCESSOR W/ INTEGRATED - Tape and Reel |
| AD9847AKST | 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Trays |
| AD9847AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V/5V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Tape and Reel |
| AD9847AKSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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