參數(shù)資料
型號: AD9826KRSZRL
廠商: Analog Devices Inc
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: IC IMAGE SGNL PROC 16BIT 28-SSOP
標準包裝: 1,500
類型: 圖像傳感器
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 75mA
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
AD9826
–12–
ANALOG
INPUTS
CDSCLK1
CDSCLK2
RED
PGA
OUT
OUTPUT
DATA
D<7:0>
PIXEL n (R,G,B)
PIXEL (n+1)
HIGH
BYTE
LOW
BYTE
ADCCLK
GREEN
PGA
OUT
BLUE
PGA
OUT
MUX
OUT
HB
LB
HB
R(n–2)
G(n–2)
B(n–2)
R(n–1)
G(n–1)
B(n–1)
R(n)
G(n)
BLUE (n–1)
GREEN (n–1)
GREEN (n)
BLUE (n)
GREEN (n+1)
RED (n+1)
GREEN (n–1)
BLUE (n–1)
RED (n–1)
RED (n)
GREEN (n)
BLUE (n)
RED (n+1)
GREEN (n+1)
BLUE (n+1)
RED (n)
NOTES
1.THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE.
2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE.
3. AFTER CDSCLK2 RISING EDGE,THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT.
4.THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES.
5.THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.
Figure 11. Internal Timing Diagram for 3-Channel CDS Mode
REV. B
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