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參數(shù)資料
型號： AD9779BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 27/56頁
文件大?。?/td> 0K
描述： IC DAC 16BIT DUAL 1GSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776/AD9778/AD9779
Rev. A | Page 33 of 56
10
–100
–4
4
–3
–2
–1
0123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
fOUT (× Input Data Rate)
ATTE
NUATION
(dB)
05361-062
Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter
10
–100
–4
4
–3
–2
–1
0
1
2
3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
fOUT (× Input Data Rate)
AT
T
E
N
UAT
IO
N
(
d
B
)
05
36
1-
06
3
Figure 66. Interpolation/Modulation Combination of
2 fDAC/8 Filter in Shifted Mode
10
–100
–4
4
–3
–2
–1
0123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
fOUT (× Input Data Rate)
ATTE
NUATION
(dB)
05361-064
Figure 67. Interpolation/Modulation Combination of
3 fDAC/8 Filter in Shifted Mode
Shifted mode filter responses allow the pass band to be centered
around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching
to the shifted mode response does not modulate the signal.
Instead, the pass band is simply shifted. For example, picture
the response shown in Figure 67 and assume the signal in-band
is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If
the even mode filter response is then selected, the pass band
becomes centered at 3.5 fDATA. However, the signal remains at
the same place in the spectrum. The shifted mode capability
allows the filter pass band to be placed anywhere in the DAC
Nyquist bandwidth.
The AD9776/AD9778/AD9779 are dual DACs with internal
complex modulators built into the interpolating filter response.
In dual channel mode, the devices expect the real and the
imaginary components of a complex signal at Digital Input
Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC
outputs then represent the real and imaginary components of
the input signal, modulated by the complex carrier fDAC/2,
fDAC/4, or fDAC/8.
With Register 2, Bit 6 set, the device accepts interleaved data on
Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved
mode, the channel data rate at the beginning of the I and the Q
data paths are now half the input data rate because of the inter-
leaving. The maximum input data rate is still subject to the
maximum specification of the device. This limits the synthesis
bandwidth available at the input in interleaved mode.
With Register 0x02, Bit 5 (real mode) set, the Q channel and the
internal I and Q digital modulation are turned off. The output
spectrum at the I DAC then represents the signal at Digital
Input Port 1, interpolated by 1×, 2×, 4×, or 8×.
The general recommendation is that if the desired signal is
within ±0.4 × fDATA, the odd filter mode should be used. Outside
of this, the even filter mode should be used. In any situation, the
total bandwidth of the signal should be less than 0.8 × fDATA.
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