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參數(shù)資料
| 型號： | AD9760-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 125 MSPS TxDAC D/A Converter |
| 中文描述： | 10位，125 MSPS的TxDAC系列D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大小： | 412K |
| 代理商： | AD9760-EB |
AD9760
–
15
–
REV. B
Note, the clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2), and
meets the min/max logic threshold. This will typically result in a
slight degradation in the phase noise, that becomes more notice-
able at higher sampling rates and output frequencies. Also, at
higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and subsequently cut into the required data
setup and hold times.
SLEEP MODE OPERATION
The AD9760 has a power-down function that turns off the out-
put current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures that the AD9760 remains enabled
if this input is left disconnected. The SLEEP input with active
pull-down requires <40
μ
A of drive current.
The power-up and power-down characteristics of the AD9760
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1
μ
F, the
AD9760 takes less than 5
μ
s to power down and approximately
3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 45.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9760 is dependent on
several factors that include: (1) AVDD and DVDD, the power
supply voltages; (2) I
OUTFS
, the full-scale current output; (3)
f
CLOCK
, the update rate; (4) and the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, I
AVDD
, and the digital supply current,
I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown in Fig-
ure 47 and is insensitive to f
CLOCK
.
I
OUTFS
–
mA
30
02
20
4
6
8
10
12
14
16
18
25
20
15
10
5
I
A
–
Figure 47. I
AVDD
vs. I
OUTFS
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 48 and 49
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3V.
RATIO (f
OUT
/f
CLK
)
18
16
0
0.01
1
0.1
I
D
–
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 48. I
DVDD
vs. Ratio @ DVDD = 5 V
RATIO (f
OUT
/f
CLK
)
8
0
0.01
1
0.1
I
D
–
6
4
2
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 49. I
DVDD
vs. Ratio @ DVDD = 3 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9760-EBZ | 功能描述:BOARD EVAL FOR AD9760 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9761 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 10-Bit TxDAC+⑩ with 2x Interpolation Filters |
| AD9761ARS | 功能描述:IC DAC 10BIT DUAL 40MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9761-ARS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| AD9761ARSRL | 功能描述:IC DAC 10BIT DUAL 40MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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