參數(shù)資料
型號(hào)： AD9760-EB
廠(chǎng)商： Analog Devices, Inc.
英文描述： 10-Bit, 125 MSPS TxDAC D/A Converter
中文描述： 10位，125 MSPS的TxDAC系列D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 13/23頁(yè)
文件大?。?/td> 412K
代理商： AD9760-EB
AD9760
–
13
–
REV. B
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1
μ
F external capacitor installed.
Thus, if I
REF
is fixed for an application, a 0.1
μ
F ceramic chip
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
There are two methods in which I
REF
can be varied for a fixed
R
SET
. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, allowing I
REF
to be varied for a fixed R
SET
. Since the
input impedance of REFIO is approximately 1 M
, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 43 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
REF
is
varied by an external voltage, V
GC
, applied to R
SET
via an ampli-
fier. An example of this method is shown in Figure 44 where
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
GC
, is
referenced to ACOM and should not exceed 1.2 V. The value
of R
SET
is such that I
REFMAX
and I
REFMIN
do not exceed 62.5
μ
A
and 625
μ
A, respectively. The associated equations in Figure 44
can be used to determine the value of R
SET
.
50pF
COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9760
I
REF
OPTIONAL
BANDLIMITING
CAPACITOR
V
GC
1 F
I
REF
= (1.2
–
V
GC
)/R
SET
WITH V
GC
< V
REFIO
AND 62.5 A I
REF
625A
Figure 44. Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external con-
trol amplifier to enhance the multiplying bandwidth, distortion
performance and/or settling time. External amplifiers capable of
driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.
50pF COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9760
V
REF
INPUT
EXTERNAL
CONTROL AMPLIFIER
Figure 45. Configuring an External Reference Control
Amplifier
ANALOG OUTPUTS
The AD9760 produces two complementary current outputs,
I
OUTA
and I
OUTB
, which may be configured for single-ended or
differential operation. I
OUTA
and I
OUTB
can be converted into
complementary single-ended voltage outputs, V
OUTA
and V
OUTB
,
via a load resistor, R
LOAD
, as described in the DAC Transfer
Function section by Equations 5 through 8. The differential
voltage, V
DIFF
, existing between V
OUTA
and V
OUTB
can also be
converted to a single-ended voltage via a transformer or differ-
ential amplifier configuration. The ac performance of the AD9760
is optimum and specified using a differential transformer
coupled output in which the voltage swing at I
OUTA
and I
OUTB
is
limited to
±
0.5 V. If a single-ended unipolar output is desirable,
I
OUTA
should be selected.
The distortion and noise performance of the AD9760 can be
enhanced when the AD9760 is configured for differential opera-
tion. The common-mode error sources of both I
OUTA
and I
OUTB
can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
1.2V
50pF
COMP1
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9760
I
REF
=
V
REF
/R
SET
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
V
REF
V
DD
R
FB
OUT1
OUT2
AGND
DB7
–
DB0
AD7524
AD1580
0.1V TO 1.2V
Figure 43. Single-Supply Gain Control Circuit
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